Stacked Memory Cube Inductor Layout for Contactless Chip Communication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor modules face challenges in reducing power consumption and increasing memory capacity while maintaining thermal conductivity and heat removal efficiency due to limitations in chip design and communication methods, particularly in contactless communication between stacked chips.
Innovation Solution
A semiconductor module design featuring inductors arranged in a triangular shape perpendicular to the chip surface, allowing for contactless communication and reduced wiring resistance, with inductors on stacked memory chips and logic chips facing each other at a 90-degree angle, enabling efficient data transfer and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If memory chips are stacked vertically using TSV or micro bump to reduce power consumption, then power consumption is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent replaces the mechanical electrical connection system (TSV, micro bump) with a contactless electromagnetic induction system. Inductors are arranged on the chip surfaces to enable wireless data transmission, eliminating the need for complex through-silicon vias and bump structures while reducing power consumption.
Solution Approach 2:
The patent introduces inductors as intermediary elements that enable contactless communication between stacked chips. These inductors act as mediators that transfer data through electromagnetic fields without requiring direct physical contact or complex wiring structures.
2Ease of manufacture
If inductors are arranged in conventional patterns on chip surfaces, then manufacturing is simplified, but parasitic capacitance increases and data transfer efficiency decreases
Solution Approach 1:
The patent employs asymmetric inductor arrangements where the distance between opposing inductors varies across the chip surface. This asymmetric configuration optimizes magnetic coupling while minimizing parasitic capacitance, achieving both low energy loss and manufacturability.
Solution Approach 2:
The patent applies different inductor spacing configurations to different regions of the chip. Areas with higher data transfer requirements have optimized inductor distances, while other regions use standard spacing, allowing local optimization of parasitic capacitance without compromising overall manufacturability.
3Quantity of substance
If chip size is increased to accommodate more memory capacity, then memory capacity increases, but thermal conductivity and heat removal efficiency decrease
Solution Approach 1:
The patent transitions from two-dimensional chip expansion to three-dimensional stacked architecture. By stacking multiple chips vertically with contactless communication between layers, memory capacity increases without proportionally increasing the footprint area, thereby maintaining thermal conductivity and heat removal efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves lower power consumption, higher data transfer rates, and improved thermal conductivity by minimizing thermal resistance and parasitic capacitance, allowing for larger memory capacity without increasing chip size.
Implementation Method 1
the first inductor and the second inductor are capable of contactless communication
Data Source
AI summary
The semiconductor module includes a semiconductor chip including a first surface parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first surface, and a memory cube including a plurality of memory chips stacked in the first direction and arranged on the second surface. Each of the plurality of memory chips includes a first inductor arranged in a third direction perpendicular to the first direction and the second direction. The semiconductor chip includes a second inductor arranged parallel to the second surface. The first inductor includes a first side and a second side extending in the third direction. The distance between the first side and the second side cut parallel to the second surface becomes shorter as the distance from the second surface increases in the third direction. The first inductor and the second inductor are capable of contactless communication.