3D Memory Cube Power Routing With Thick Passive Wiring
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Solution Overview
Problem
Current high bandwidth 3D memory cube structures face challenges in power delivery due to thin wiring, leading to significant I2R power loss and voltage drop, which affects performance and requires higher power supply, especially when routing power signals to logic devices.
Innovation Solution
Incorporation of non-semiconductor passive chips, such as glass or dielectric oxide chips, with thick conductive wiring and voltage step-down circuits to manage power delivery efficiently, along with decoupling capacitors and inductors, forming a stack with semiconductor memory slices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If thin wiring is used to route power signals through memory chips, then device complexity is reduced and manufacturing is simplified, but I2R power loss increases significantly
Solution Approach 1:
The patent divides the power delivery function into separate components: thin wiring for signal routing and thick wiring for power delivery. This segmentation allows each component to be optimized for its specific function, reducing overall power loss while maintaining manufacturing simplicity.
Solution Approach 2:
The patent introduces an intermediary thick wiring layer that acts as a power delivery mediator between the power source and logic elements. This thick wiring serves as a dedicated power highway, reducing I2R losses without complicating the existing thin wiring signal routing infrastructure.
2Manufacturing precision
If thin wiring is used for power routing, then manufacturing precision requirements are reduced, but voltage drop increases affecting performance
Solution Approach 1:
The power delivery system is segmented into thick wiring for voltage/Power delivery and thin wiring for signal routing. This segmentation ensures that voltage drop-critical power paths use robust thick conductors with relaxed manufacturing tolerances, while signal paths maintain existing precision requirements.
Solution Approach 2:
Different wiring regions are assigned different qualities: thick wiring with high power carrying capacity for power delivery paths, and thin wiring with fine precision for signal paths. This local quality differentiation optimizes both manufacturing ease and voltage delivery stability in their respective domains.
3Reliability
If higher power supply is used to compensate for power loss, then logic element performance is maintained, but energy efficiency deteriorates
Solution Approach 1:
The patent converts the potential harm of power loss into a benefit by using thick wiring to create dedicated low-loss power paths. This transforms the power delivery challenge into an opportunity to implement efficient power highways that reduce overall system power consumption while maintaining logic element performance.
Solution Approach 2:
The patent changes the wiring thickness parameter specifically for power delivery paths, increasing conductor cross-section to reduce resistance. This parameter change directly reduces I2R losses and improves power delivery efficiency without affecting signal routing functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures efficient power delivery and energy-efficient computing by minimizing power loss and enabling integration of 3D memory cubes in high-performance chiplet strategies, supporting applications like AI and high-end computing.
Implementation Method 1
one or more vertically-oriented passive slices having a conductive wire element disposed thereon for delivering power signals from a power source
Implementation Method 2
Additionally, the non-semiconductor passive chip or a passive or active Si chip having a thick wire for improved power delivery can be further contained with decoupling capacitors ('decaps'), inductors and voltage regulators
Implementation Method 3
Additionally, the non-semiconductor passive chip or a passive or active Si chip having a thick wire for improved power delivery can be further contained with decoupling capacitors ('decaps'), inductors and voltage regulators
Data Source
AI summary
A high bandwidth 3D memory cube structure having one or more passive chip structures such as a glass chip, a dielectric oxide chip or a Si chip having a thick conductive wiring formed thereon that is dedicated for routing power signals for improved power delivery. The non-semiconductor passive chip or Si chip having a thick wiring fabricated thereon is dedicated for routing power signals to another component connected to the high bandwidth memory cube such as a voltage step-down circuit or like power management device, a processing logic device, or an interposer. The voltage step down circuit can interfaces with the memory cube structure at a top edge thereof. The provision of a glass or a Si substrate with thick wiring and voltage step down circuitry in the high bandwidth 3D memory cube structure, solves power management challenges and enables customization of standard DRAM, fixed wiring and I/O footprint.