Nonvolatile Memory Device Current Limit Circuit
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Solution Overview
Problem
In nonvolatile semiconductor memory devices, particularly in ReRAM, the controllability of memory cells is compromised due to excessive Joule heat during programming and voltage regulator limitations, leading to unintended state changes during data write and erase operations.
Innovation Solution
Incorporating a current limit circuit to regulate the current during data write, a charge limit circuit to manage charge supply during data write, and a voltage clamp circuit to control the erase voltage, ensuring precise voltage and current management to prevent unwanted state changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a program voltage is applied to change the memory cell from high-resistance state to low-resistance state, then data programming is achieved, but excessive Joule heat causes the memory cell to reset to high-resistance state
Solution Approach 1:
A current limit circuit is introduced as an intermediary component between the data write circuit and the memory cell. This circuit mediates the current flow to ensure it does not exceed a predetermined threshold, thereby preventing excessive Joule heat generation while still enabling effective data programming of the memory cell.
Solution Approach 2:
The patent changes the current parameter by introducing a current limit circuit that constrains the current flowing through the memory cell to remain below a predetermined value. This parameter control prevents the current from reaching levels that would generate excessive Joule heat and cause unintended reset, while still maintaining sufficient current for reliable programming.
2Reliability
If an erase voltage is applied to change the memory cell from low-resistance state to high-resistance state, then data erasing is achieved, but voltage regulator cannot follow the speed change causing excessive charge supply and voltage overshoot
Solution Approach 1:
A voltage clamp circuit is introduced as an intermediary component that mediates the voltage applied to the memory cell during erase operations. This circuit ensures the voltage does not exceed a predetermined threshold, preventing voltage overshoot caused by the voltage regulator's inability to respond quickly enough to rapid state changes.
Solution Approach 2:
The patent changes the voltage parameter by introducing a voltage clamp circuit that constrains the voltage applied to the memory cell to remain below a predetermined value. This parameter control prevents voltage overshoot and excessive charge supply that occur when the voltage regulator cannot respond fast enough to rapid resistance state changes during erasing.
3Productivity
If current is not limited during data write, then programming speed is maintained, but memory cell state becomes uncontrollable due to unintended resets
Solution Approach 1:
The patent applies parameter change by setting a predetermined current limit that allows sufficient current flow to maintain programming speed while preventing the current from reaching levels that cause unintended resets. The current limit circuit dynamically controls the current parameter to balance speed and controllability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These circuits effectively prevent unintended resets and ensure reliable data programming and erasing by limiting current, charge, and voltage, thereby enhancing the controllability and reliability of memory cell states.
Implementation Method 1
the memory cell once changed into the low-resistance state is again reset to the high-resistance state due to production of Joule heat
Implementation Method 2
the supply of charge becomes excessive, the voltage of the applied pulse becomes higher
Data Source
AI summary
A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistive element; a data write circuit operative to apply a voltage required for data write to the memory cell via the first and second lines; and a current limit circuit operative to limit the value of current flowing in the memory cell on the data write at a certain current limit value.