Nonvolatile Memory Current Limiting Circuit Reliability
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Solution Overview
Problem
In unipolar-type ReRAM, excessive pulse application during state changes leads to uncontrollable memory cell transitions due to Joule heat and voltage regulator limitations, causing failed resets and write errors.
Innovation Solution
Implementing a current limiting circuitry that restricts current flow in both bit-line and word-line circuits, using a combination of current limit circuits and charge management circuits to control the current and voltage applied to memory cells, thereby preventing excessive state changes and improving controllability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a program voltage is applied to change the memory cell state, then the memory cell transitions from high-resistance to low-resistance state, but excessive pulse application causes the memory cell to reset again due to Joule heat
Solution Approach 1:
The patent converts the harmful Joule heat effect into a beneficial mechanism by using it to trigger the reset operation. When the memory cell transitions to low-resistance state, the accumulated Joule heat automatically triggers a reset pulse that changes the state back to high-resistance, preventing excessive heat accumulation and enabling reliable state control without external intervention.
2Speed
If an erase voltage is applied to change the memory cell from low-resistance to high-resistance state, then the state change occurs, but the voltage regulator cannot follow the speed of state change, causing excessive charge supply and voltage increase
Solution Approach 1:
The patent implements a feedback mechanism where the voltage regulator monitors the actual voltage across the memory cell during state transitions. When the memory cell rapidly changes state, the feedback signal adjusts the regulator output to prevent excessive charge supply, maintaining voltage controllability even at high state change speeds.
3Reliability
If current limiting is applied to the anode-side line to prevent failed write, then the current flowing in the selected memory cell is limited, but the charge accumulated in parasitic capacity leaks to the memory cell, limiting the current limiting effect
Solution Approach 1:
The patent applies preliminary action by pre-charging the parasitic capacity through a dedicated charge pump circuit before the write operation begins. This preliminary charging ensures that when the write current is limited, the parasitic capacity does not steal additional charge from the memory cell, maintaining the effectiveness of the current limiting mechanism throughout the operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The current limiting approach enhances the reliability of memory cell state transitions, reducing the likelihood of failed writes and resets, and improves the overall performance of the nonvolatile memory device by maintaining the low-resistance and high-resistance states effectively.
Implementation Method 1
the memory cell once changed into the low-resistance state is reset again to the high-resistance state due to production of Joule heat
Data Source
AI summary
A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell array including plural mutually crossing first and second lines and memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistance element and a rectifier element connected in series; and a data write/erase circuit operative to apply a voltage required for data write/erase to the memory cell via the first and second lines. The data write/erase circuit includes a first current limit circuit operative to limit the current flowing in the cathode-side line provided on the cathode side of the rectifier element, of the first and second lines, at the time of data write/erase.