3D Semiconductor Memory Cutting-Line Layout for Dense Vertical Cells
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Solution Overview
Problem
Current two-dimensional semiconductor devices face limitations in integration density due to the need for expensive equipment for miniaturization, which restricts their performance and cost-effectiveness, prompting the development of three-dimensional semiconductor memory devices with vertically arranged memory cells.
Innovation Solution
A semiconductor memory device with a stacked structure featuring metallic lines, a semiconductor conduction line, and a vertical channel structure, including a channel film and cutting lines, where the channel film has upper and lower components connected by an upper connection channel film, and the cutting lines have distinct widths to enhance integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional planar semiconductor devices are used, then manufacturing process is simpler, but degree of integration is limited and expensive equipment is required for miniaturization
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction (first direction), with metallic lines and channel films arranged in three dimensions. This dimensional change increases degree of integration without requiring further miniaturization of two-dimensional patterns, thereby avoiding the need for expensive ultra-fine pattern formation equipment.
2Manufacturing precision
If pattern miniaturization is pursued in two-dimensional devices, then degree of integration increases, but expensive ultra-expensive apparatuses are required
Solution Approach 1:
Instead of continuing to miniaturize two-dimensional patterns which requires expensive equipment, the patent stacks multiple memory cell layers vertically in the first direction. The metallic lines and channel films are formed with standard patterning techniques, then stacked using layer-by-layer deposition and etching processes. This approach achieves high integration density through vertical stacking rather than horizontal miniaturization, significantly reducing manufacturing equipment costs.
3Manufacturing precision
If three-dimensional stacked structure is implemented, then degree of integration increases, but device structure becomes more complex
Solution Approach 1:
The three-dimensional memory structure is segmented into multiple identical or similar memory cell layers stacked in the first direction. Each layer contains metallic lines, channel films, and insulation films arranged in a repeating pattern. This segmentation allows the complex 3D structure to be built from simpler repeating units, facilitating manufacturing through standardized layer-by-layer processes while achieving high integration density.
Solution Approach 2:
The patent employs a nested structure where multiple memory cell layers are stacked within a three-dimensional space. The channel films are positioned between metallic lines in each layer, with connection channel films extending in the second direction to connect corresponding elements across layers. This nested arrangement efficiently utilizes three-dimensional space to increase integration density while maintaining a systematic and manufacturable structure.
Data Source
AI summary
A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.