Memory Device Cycle Timing with Recovery-Period Cache Access
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Solution Overview
Problem
Semiconductor devices face challenges in achieving higher read frequencies due to the need to align read control timing with worst-case performance, which limits the use of higher read frequencies for improved performance.
Innovation Solution
Implementing a method in semiconductor devices that allows for starting a second operation cycle immediately after the recovery period of a first cycle when a command is received before the end of the first recovery period, reducing the time period of the second cycle and eliminating the need for a voltage set period, thereby increasing data access speed and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read control timing is aligned with worst read performance, then read reliability is ensured, but read frequency is suppressed and cannot be increased for higher performance
Solution Approach 1:
The patent dynamically adjusts the read operation cycle length based on actual read performance rather than using a fixed worst-case timing. The controller monitors read completion status and adapts the timing parameters accordingly, allowing the system to transition from static worst-case alignment to dynamic performance-based timing optimization.
Solution Approach 2:
The patent changes the timing parameters of read operations by eliminating unnecessary periods (voltage set period, operation set period) and adjusting recovery periods based on actual device performance. This parameter optimization allows higher read frequencies while maintaining reliability through adaptive timing rather than conservative fixed timing.
2Reliability
If a second operation cycle waits for the first operation recovery period to complete, then operation reliability is maintained, but operation latency increases and throughput decreases
Solution Approach 1:
The patent prepares the cache and voltage levels in advance during the first operation's recovery period, so that when the second operation command arrives, the device can immediately start the second operation cycle without waiting for full recovery. This preliminary preparation enables overlapping operations and reduces idle time.
Solution Approach 2:
The patent maintains continuous operation currents and eliminates idle gaps between operation cycles by optimizing the recovery period utilization. The cache remains active and ready throughout what would traditionally be a recovery wait period, ensuring continuous useful action rather than intermittent operation with idle gaps.
3Stability of the object's composition
If voltage set period and operation set period are included in each operation cycle, then operation stability is ensured, but operation cycle length increases and reduces throughput
Solution Approach 1:
The patent extracts and removes the voltage set period and operation set period from the standard operation cycle, determining that these periods are unnecessary for achieving stable operations. By eliminating these redundant periods while maintaining essential recovery time, the cycle length is reduced and throughput is increased without sacrificing operational stability.
Solution Approach 2:
The patent discards the traditional voltage set and operation set periods that were previously considered necessary for stability. Instead, it recovers the essential stability function through optimized recovery period management and cache timing, achieving the same stability outcome with fewer and shorter operation phases.
Data Source
AI summary
An operation method for a memory device comprises: starts a first operation cycle after receiving a first operation command, the first operation cycle including a voltage set period, a first operation set period, a first operation executing period and a first operation recovery period; when a second operation command is received by the memory device before the end of the first operation recovery period, starts a second operation cycle directly after the end of the first operation recovery period. The second operation cycle includes a second operation set period, a second operation executing period and a second operation recovery period, and the second operation set period is adjacent to the first operation recovery period. The cache is switched to a ready status from a busy status while starting the first operation recovery period and the second operation recovery period, such that data in the cache is accessible.