Stepped 3D Memory Stack With Dam Plugs for Reliable Interconnects
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high data storage capacity and integration density while maintaining reliability, particularly in three-dimensionally arranged memory cell structures.
Innovation Solution
The semiconductor device incorporates a peripheral circuit structure on a semiconductor substrate with a stepwise electrode stack, a planarization insulating layer, vertical data storage patterns, separation structures, and a dam group with insulating dams and penetration plugs to enhance integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arranged to increase data storage capacity, then integration density is improved, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The device is divided into distinct functional regions: a cell array region for data storage and a connection region for peripheral circuit connections. This segmentation allows independent optimization of each region, enabling high-density 3D memory structures in the cell array while maintaining manufacturing precision in the connection region through separate process control.
Solution Approach 2:
Different structural configurations are applied to different regions: the cell array region employs vertically stacked memory cells for maximum density, while the connection region uses a stepped electrode structure with varying thicknesses to facilitate reliable peripheral circuit integration. This local differentiation resolves the contradiction by allowing each region to be optimized for its specific function.
2Quantity of substance
If memory cells are three-dimensionally arranged to increase integration density, then data storage capacity is improved, but device reliability deteriorates
Solution Approach 1:
The device separates data storage functions (3D stacked cells in cell array region) from connection functions (peripheral circuits in connection region), allowing the reliable peripheral circuits to remain in a lower-density configuration while achieving high integration density in the storage region through vertical stacking of memory cells.
Solution Approach 2:
The invention transitions from two-dimensional planar arrangements to three-dimensional vertical stacking in the cell array region, increasing integration density by utilizing the vertical dimension. Meanwhile, the connection region maintains a more conventional stepped structure that ensures reliable electrical connections, thus resolving the reliability concern while achieving high density.
3Quantity of substance
If electrode stacks are made with varying thicknesses to improve integration density, then manufacturing complexity increases
Solution Approach 1:
The electrode structure implements local quality variation: the first electrode has a first thickness in the cell array region and a second thickness in the connection region, while the second electrode has a third thickness in the cell array region and a fourth thickness in the connection region. This localized thickness variation optimizes integration density in the cell array while maintaining manufacturability in the connection region.
Solution Approach 2:
The electrode stack is segmented into multiple electrodes with different thickness profiles in different regions. This segmentation allows each electrode to be independently optimized for its local function, managing device complexity by breaking down the overall structure into manageable segments with specific purposes.
Data Source
AI summary
A peripheral circuit structure may include peripheral circuits and peripheral circuit lines on a semiconductor substrate, a semiconductor layer including cell array and connection regions on the peripheral circuit structure, a stack including electrodes stacked on the semiconductor layer having a stepwise structure on the connection region, and a planarization insulating layer covering the stack, vertical structures on the cell array region penetrating the stack, including a data storage pattern, a dam group including insulating dams on the connection region penetrating the stack, penetration plugs penetrating the insulating dams and connected to respective peripheral circuit lines, the dam group including a first insulating dam farthest from the cell array region, the first insulating dam including first and second sidewall portions spaced apart, a difference between upper and lower thicknesses of the second sidewall portion of the first insulating dam is larger than that of the first sidewall portion.