3D Memory Dam Region Layout for Through-Via Stress Relief

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Solution Overview

Problem

The integration of semiconductor memory devices is limited by cost and manufacturing factors, particularly in two-dimensional designs, while three-dimensional devices face challenges in maintaining product reliability due to stress-induced buckling in dam regions.

Innovation Solution

A semiconductor memory device design featuring a mold structure with alternately stacked insulation films and gate electrodes, including a through via in a closed-loop dam region that reduces stress by having a separate, spaced-apart dam region without a through via, improving product reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a through via is formed in the dam region to connect gate electrodes with peripheral circuits, then electrical connectivity is improved, but stress concentration occurs causing buckling and reducing product reliability

Engineering Contradiction:

Improveproduct reliabilityVSAvoidstress-induced buckling

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The dam region is divided into two separate regions: a first dam region containing the through via for electrical connectivity, and a second dam region without a through via to serve as a stress-free reference structure. This segmentation prevents stress concentration in a single location, eliminating buckling while maintaining electrical connectivity through the first dam region.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different structural qualities are applied to different dam regions: the first dam region has a through via for electrical connection purposes, while the second dam region is designed without a through via to maintain structural integrity and serve as a stress reference. This local differentiation allows the system to achieve both electrical connectivity and stress management.

Inventive Principle:

Principle #3Local quality

2Area of moving object

If two-dimensional memory cell patterns are miniaturized to increase integration density, then area occupancy is reduced, but manufacturing cost increases due to expensive fine pattern forming apparatus

Engineering Contradiction:

Improvearea occupied by unit memory cellVSAvoidmanufacturing cost

Core Design Contradiction:

Area of moving objectVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional planar memory cell arrangements to three-dimensional vertical stacking of memory cells. This dimensional change allows integration density to increase without requiring further miniaturization of the lateral pattern dimensions, thereby avoiding the need for expensive fine pattern forming apparatus while still achieving high density.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12199043B2Semiconductor memory devices, methods for fabricating the same and electronic systems including the same

Publication Date: 2025.01.14 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor memory device may include a mold structure that includes mold insulation films and gate electrodes alternately stacked on a first substrate, a channel structure that penetrates the mold structure and intersects the gate electrodes, a block separation region that extends in a first direction parallel to an upper surface of the first substrate and cuts the mold structure, a first dam region and a second dam region spaced apart from each other, that each having a closed loop in a plan view and each cutting the mold structure, pad insulation films in the first and second dam regions that are alternately stacked with the mold insulation films and include a material different from the mold insulation films, and a through via which penetrates through the first substrate, the mold insulation films, and the pad insulation films, in the first dam region but not in the second dam region.