Semiconductor Memory Data Buffering and Error Propagation Control

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Solution Overview

Problem

Conventional semiconductor memory devices face challenges in preventing write errors from propagating to stored data, especially when data is not buffered, leading to data corruption and inability to recover data during power disconnection or errors.

Innovation Solution

A semiconductor memory system with a host device and memory manager that includes a data buffer, block boundary manager, and error propagation detector to manage data writing, detect errors, and reissue write commands to prevent data destruction, utilizing a logical-physical conversion table to handle multi-level flash memory blocks and requesting new blocks for secure writing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is written to nonvolatile memory without buffering, then writing speed is improved, but write errors can propagate to stored data causing data corruption

Engineering Contradiction:
Improvewriting speedVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent segments the data writing process into distinct phases: pre-write buffering of data, error detection during writing, and selective re-writing based on error propagation detection. This segmentation allows the system to maintain high writing speeds while preventing error propagation to stored data by isolating potential errors to specific segments that can be corrected without affecting other data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary error propagation detection mechanism between the data buffer and the nonvolatile memory. This intermediary detects whether write errors propagate to stored data and provides feedback to control the re-writing process, thereby preventing data corruption while maintaining efficient writing operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If data is buffered during writing, then error propagation can be prevented, but data recovery capability is reduced when power disconnection occurs

Engineering Contradiction:
Improveerror propagation preventionVSAvoiddata recoverability
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent implements preliminary buffering of data before writing to nonvolatile memory. This preliminary action ensures that data is prepared and protected in a recoverable state, enabling data recovery even if power disconnection occurs during the writing process. The buffer acts as a safety net that preserves data integrity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs a feedback mechanism where the error propagation detector monitors the writing process and provides feedback to the control system. This feedback enables the system to detect errors, determine their impact on stored data, and initiate appropriate recovery procedures, thereby maintaining both error prevention and data recoverability.

Inventive Principle:
Principle #23Feedback

3Quantity of substance

If multi-level flash memory is used to increase capacity, then storage density is improved, but error propagation to stored data becomes more complex

Engineering Contradiction:
Improvestorage capacityVSAvoiderror propagation complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies local quality by detecting and addressing error propagation at specific local levels within the multi-level flash memory structure. Instead of treating all memory cells uniformly, the system identifies which specific cell levels are affected by write errors and applies targeted correction only to those local areas, thereby managing the complexity introduced by multi-level storage.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces dynamic error propagation detection and correction mechanisms that adapt to the specific conditions of multi-level flash memory operations. The system dynamically determines the extent of error propagation based on the current writing operation and memory state, allowing flexible management of complexity in high-capacity storage systems.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8352807B2Semiconductor memory device, host device and semiconductor memory system
Publication Date: 2013.01.08 PANASONIC HOLDINGS CORP
  • US8352807B2 patent drawing
  • US8352807B2 patent drawing
  • US8352807B2 patent drawing

AI summary

A host device 200A includes a data buffer 250. When data has been already written to a part of a physical block and data is additionally written to the physical block, it is determined whether or not the data written to the physical block is held in the data buffer. When the data is held, data is written to the block, and when an error exists, data in unit of physical blocks is rewritten. When the data is not held in the data buffer, a new physical block is required to be secured and then, data is written to the new block. Thereby, even when power is shut off or an error occurs during writing in the semiconductor memory device, destruction of data already written is prevented.