Semiconductor Memory Data Bus Inversion for Current Reduction
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Solution Overview
Problem
Conventional semiconductor memory apparatuses operating at high frequencies face noise-related performance deterioration and substantial current consumption due to frequent data switching, and the data bus inversion scheme has limitations in reducing current consumption and interfacing issues between the memory apparatus and chipset.
Innovation Solution
A semiconductor memory apparatus with input and output data bus inversion units that determine whether to invert data based on logic levels, generating conversion data to reduce current consumption and ensure accurate data storage and output, while allowing inversion operations in both DBI and normal modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data bus inversion is performed only in DBI mode through mode signal control, then interfacing between memory apparatus and chipset is maintained, but current consumption cannot be reduced in normal mode operations
Solution Approach 1:
The data bus inversion units are designed to perform inversion operations in both DBI mode and normal mode, making the inversion functionality universal across different operating modes. The determination units continuously monitor data patterns and perform inversion whenever beneficial, regardless of mode signal state, thus reducing current consumption in all operational contexts while maintaining chipset interfacing compatibility.
2Use of energy by moving object
If data inversion is performed based on logic levels to reduce current consumption, then energy efficiency is improved, but data transmission complexity increases
Solution Approach 1:
Data bus inversion determination units are introduced as intermediary components between the data source and data transmission path. These determination units analyze data patterns and control the inversion operation, acting as a mediator that automatically manages the complexity of data transmission while enabling current consumption reduction through selective inversion based on logic level analysis.
3Speed
If the number of data switching times is increased to improve data processing speed, then processing performance is improved, but noise generation and misoperation increase
Solution Approach 1:
Instead of simply increasing data switching times to improve processing speed, the invention applies data bus inversion technology that inverts data patterns to reduce unnecessary switching. By analyzing data patterns and inverting when beneficial, the system reduces the actual number of transitions occurring on the bus, thereby reducing noise and misoperation while maintaining effective data processing throughput.
Data Source
AI summary
A semiconductor memory apparatus includes an input data bus inversion unit configured to determine whether or not to invert a plurality of input data depending upon levels of the plurality of input data, and generate a plurality of conversion data; data input lines configured to transmit the plurality of conversion data; a data recovery unit configured to receive the plurality of conversion data and generate a plurality of storage data; and a memory bank configured to store the plurality of storage data.