Non-Volatile Memory Data Layout for Charge-Loss Resilience

The patent implements redundant storage by creating copies of system data in pairs of non-volatile memory cells. Each system data bit is stored in two separate memory cells, and during read operations, both cells are read and processed through logic operations (AND or OR) to retrieve the original data. This copying approach ensures that if one cell becomes corrupted due to charge loss or disturb effects, the other cell can still provide the correct data, thereby improving reliability while maintaining a manageable increase in device complexity through systematic duplication.

The patent introduces logic circuits (AND or OR gates) as intermediaries between the redundant memory cell pairs and the data output. These logic circuits process the readings from both memory cells to retrieve the original system data. By using these intermediary logic elements, the patent achieves error correction functionality without requiring extremely precise manufacturing tolerances on the memory cells themselves, as the logic circuits can tolerate certain variations and still correctly determine the stored data value.

The patent employs a single sense amplifier that serves multiple functions by reading both cells in a redundant pair sequentially or simultaneously through multiplexing. The sense amplifier is controlled to first read one cell, then read the second cell, and the outputs are processed through logic circuits to determine the final data value. This multi-functional approach allows the system to achieve the measurement precision needed for reliable data retrieval while avoiding the need for separate dedicated sense amplifiers for each cell, thereby controlling device complexity.