Memory Data Circuit Time-Division Transmission
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Solution Overview
Problem
Data transmission circuits in semiconductor memory devices face challenges in maintaining uniform margins of parallel data divided by time division and suffer from high power consumption due to constant clock counting, especially in read operations using the 8-bit prefetch method.
Innovation Solution
The proposed data transmitting and receiving circuit employs delay units that generate delayed control signals based on CAS latency to time-divide and transmit data, reducing the number of transmission lines and power consumption by determining the clock frequency according to the operation frequency of the semiconductor memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the 8-bit prefetch method is used to increase data transmission speed, then the operation speed of the memory device is improved, but the number of internal data transmission lines increases, leading to increased device complexity and power consumption
Solution Approach 1:
The 8-bit prefetched data is divided into two groups of 4-bit data based on time division. The output driver sequentially outputs these divided data groups in response to control signals, reducing the required transmission lines from 8 to 4 lines while maintaining the 8-bit prefetch capability.
Solution Approach 2:
The output driver operates periodically by sequentially outputting the first 4-bit data in response to a first control signal and the second 4-bit data in response to a second control signal. This periodic action allows the system to transmit 8-bit data through 4 transmission lines over two clock cycles.
2Speed
If the 8-bit prefetch method is used to increase data transmission speed, then the operation speed of the memory device is improved, but the power consumption increases due to constant clock counting
Solution Approach 1:
The delay unit dynamically adjusts the delay time of the second control signal based on the operation frequency of the semiconductor memory device. By determining the delay time according to the operation frequency, the system optimizes power consumption while maintaining correct timing for data transmission.
Solution Approach 2:
The delay time parameter of the second control signal is changed based on the operation frequency. When the operation frequency changes, the delay unit adjusts the delay time accordingly, allowing the system to adapt to different operating conditions and optimize power consumption.
3Device complexity
If parallel data is divided based on time division to reduce the number of transmission lines, then the device complexity is reduced, but the uniformity of data margins is compromised, leading to transmission errors
Solution Approach 1:
The delay unit uses feedback from the operation frequency to adjust the delay time of the second control signal. This feedback mechanism ensures that the timing margins for both 4-bit data groups remain uniform, preventing transmission errors while maintaining the reduced transmission line configuration.
4Device complexity
If the number of transmission lines is reduced through time division, then the device complexity and power consumption are reduced, but the data transmission speed may be affected
Solution Approach 1:
The output driver sequentially outputs 4-bit data groups in response to periodic control signals. Although the transmission is divided into two sequential operations, the overall data transmission speed maintains the 8-bit prefetch capability by completing both 4-bit transmissions within the expected time frame.
Data Source
AI summary
A data receiving circuit includes a delay unit for outputting a delayed control signal by delaying a control signal based on a CAS latency, an output driver for time-dividing parallel data based on the control signal and the delayed control signal to generate divided parallel data, and for writing and transmitting the divided parallel data, and a latch for receiving the parallel data from the output driver and sorting, by combining or dividing, the received parallel data in response to the control signal and the delayed control signal.