Semiconductor Memory Data Compression Test Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data compression tests in semiconductor memory devices cannot accurately determine failures in data lines between the input buffer and global line driver or pipe latch and output driver, as these lines are not used during normal operation, leading to potential undetected failures during regular use.
Innovation Solution
A semiconductor memory device with a data compression test circuit that uses the same lines for data and comparison signal transmission during both normal and test operations, allowing for accurate failure detection by configuring data transmission units and output drivers to route signals through the same paths during both modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate test lines are used for data compression test, then test capability is provided, but failure detection accuracy deteriorates because normal operation lines are not tested
Solution Approach 1:
The data lines and output driver lines are designed to serve dual purposes: normal data transmission and data compression test. During normal operation, these lines transmit data between input buffer and global line driver, or between pipe latch and output driver. During test mode, the same lines are used to transmit test data and comparison signals, eliminating the need for separate dedicated test lines and enabling accurate failure detection in the actual operational paths.
2Measurement precision
If data are transmitted through separate test lines during compression test, then compression test can be performed, but the data lines between input buffer and global line driver cannot be tested
Solution Approach 1:
The patent merges the normal data transmission path with the test path by using the same physical lines for both functions. The data lines between input buffer and global line driver, as well as the lines between pipe latch and output driver, are combined to carry both normal data and test comparison signals. This merging allows the test to actually measure the operational paths, providing precise failure detection while maintaining operational simplicity.
3Reliability
If conventional data compression test is used, then test is performed, but undetected failures may occur during normal use
Solution Approach 1:
The test circuit generates comparison signals by comparing data from multiple cells and feeds back the results through the same lines that would be used during normal operation. This feedback mechanism allows the system to detect failures in the data lines and output drivers in real-time during compression test, ensuring that any potential failures are identified before they affect normal device operation.
Data Source
AI summary
A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal, and a transmission element configured to transmit second input data only to the second global line driver in response to the test signal.