Memory Read Output Timing with Data Eye Control
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Solution Overview
Problem
High-frequency semiconductor memory devices experience data fighting during read operations, leading to unstable data output and increased current consumption due to differing logic levels and overlapping pulse signal enablement periods.
Innovation Solution
A semiconductor memory device with a data eye control unit, comprising a delay tuning unit and phase detector, synchronizes internal clocks with delay locked clocks to control pulse signals and prevent overlapping enablement of transmission gates, maintaining a constant data eye and reducing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pulse width of the pulse signal is increased to transmit data without fail at high frequency, then data transmission reliability is improved, but transmission gates remain open for extended intervals causing data fighting and increased current consumption
Solution Approach 1:
The patent applies dynamics by making the pulse width variable rather than fixed. The pulse width is dynamically adjusted based on the data value being transmitted - using a first pulse width for logic high levels and a second pulse width for logic low levels. This dynamic adjustment allows reliable data transmission while minimizing the time transmission gates remain open, thereby reducing current consumption and preventing data fighting.
Solution Approach 2:
The patent changes the parameter of pulse width based on the logic level of the data being transmitted. By switching between different pulse width parameters (first pulse width for logic high, second pulse width for logic low), the system achieves both reliable data transmission and reduced current consumption, as the transmission gates are opened for the minimum necessary duration for each specific data condition.
2Reliability
If the pulse width is increased to ensure data transmission at high frequency, then data transmission stability is improved, but overlapping enablement periods of transmission gates cause data fighting and unstable data output
Solution Approach 1:
The patent uses dynamic pulse width adjustment to prevent overlapping enablement periods. By adapting the pulse width to the specific data value being transmitted, the system ensures that transmission gates are opened for exactly the necessary duration without extending into intervals that would cause overlap with adjacent gate operations, thereby eliminating data fighting while maintaining stable data output.
Solution Approach 2:
The patent changes the pulse width parameter based on the data logic level to prevent harmful overlapping. When data logic high level is detected, a first pulse width is used; when logic low level is detected, a second pulse width is used. This parameter adaptation ensures reliable transmission without creating the overlapping conditions that lead to data fighting and unstable output.
Data Source
AI summary
A semiconductor memory device stably performs a read operation at a high frequency, thereby reducing a current consumption. The semiconductor memory device is capable of performing the read operation stably by controlling a data eye. The semiconductor memory device includes an output unit and a data eye control unit. The output unit outputs data in synchronization with clock signals. The data eye control unit controls a data eye of the data output by the output unit.