Memory Data Forwarding Circuits With Shift-Register Address Compare
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Solution Overview
Problem
Conventional synchronous memory devices lack advanced features such as data forwarding to multiple ports and a wide range of write latency options, including long late write options, which are essential for more advanced applications.
Innovation Solution
The memory device incorporates a content addressable memory (CAM) circuit and a shift-register-like address compare section that allows for data forwarding and various write latency options by shifting stored write addresses, enabling data to be output as read data when a match is detected, and accommodating multiple ports and long late write options through a deep shift-register circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional synchronous memory devices use standard write latency options, then the device structure remains simple, but the device cannot support advanced applications requiring long late write options and data forwarding to multiple ports
Solution Approach 1:
The CAM circuit is designed to perform multiple functions: it stores write addresses, compares read addresses against stored write addresses, and enables data forwarding operations. This multi-functional design allows the same hardware structure to support various write latency options and data forwarding capabilities without requiring separate dedicated circuits for each function.
Solution Approach 2:
The patent implements a deep shift-register circuit nested within the address compare section, where the shift-register is integrated into the CAM structure. This nesting allows the system to achieve long late write options (up to 13 cycles) by shifting stored write addresses through multiple stages within the existing CAM framework, rather than requiring a completely separate delay mechanism.
2Adaptability or versatility
If the memory device supports data forwarding to multiple ports, then the versatility for advanced applications is improved, but the device complexity increases
Solution Approach 1:
The CAM circuit serves as a universal structure that handles both address comparison for standard operations and address matching for data forwarding operations. The same CAM hardware enables multiple ports to access forwarded data by comparing their read addresses against the stored write addresses, eliminating the need for separate forwarding circuits for each port.
Solution Approach 2:
The system uses its own existing CAM infrastructure to enable data forwarding functionality. Rather than adding external forwarding circuits, the patent makes the CAM circuit serve the additional function of identifying which write data should be forwarded to which ports, allowing the device to forward data using its own internal resources.
3Duration of action of moving object
If conventional memory devices use standard late write options (2-3 cycles), then the device structure remains simple, but the device cannot meet requirements for long late write options
Solution Approach 1:
The patent implements a dynamic shift-register circuit within the address compare section that can shift stored write addresses through multiple stages. This dynamic shifting mechanism allows the system to achieve variable and extended late write durations (up to 13 cycles) by controlling the number of shift stages, rather than being fixed at standard 2-3 cycle delays.
Solution Approach 2:
The patent extends the address compare section into a deep shift-register structure, adding temporal dimensionality to the address comparison process. By shifting addresses through multiple register stages over multiple clock cycles, the system creates extended time windows for late write operations without requiring parallel comparison paths.
Data Source
AI summary
A memory device can include a memory array section; a write first-in-first-out circuit (FIFO) configured to transfer write data to the memory array portion; at least one store circuit configured to store a copy of at least a portion of the write data stored in the write FIFO; and an address compare section configured to store write addresses corresponding to the write data of the forwarding circuit.