Nonvolatile Memory Data Rearrangement for Cell Interference Reduction
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Solution Overview
Problem
Multi-bit semiconductor memory devices face challenges in maintaining data reliability due to threshold voltage shifts caused by factors like thermionic emission, charge diffusion, and program disturbance, leading to increased interference between memory cells.
Innovation Solution
Implementing a data processing method that uses error correction codes (ECC) to rearrange data and add parity, specifically through non-systematic ECC operations, to reduce interference between memory cells and stabilize threshold voltages in nonvolatile memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit memory cells are used to increase storage density, then integration density is improved, but threshold voltage shifts due to charge diffusion and program disturbance increase, worsening data retention characteristics
Solution Approach 1:
The memory array is divided into multiple blocks, and data is distributed across different blocks through block interleaving. This segmentation prevents concentration of interference effects in a single location, thereby reducing the impact of threshold voltage shifts on overall data retention while maintaining high storage density through multi-bit memory cells.
Solution Approach 2:
An error correction code (ECC) system is introduced as an intermediary mechanism to detect and correct threshold voltage shifts caused by charge diffusion and program disturbance. The ECC encoder adds redundancy bits to data before storage, and the ECC decoder corrects errors after retrieval, thereby compensating for reliability degradation while maintaining high storage density.
2Quantity of substance
If adjacent memory cells are programmed with conflicting states, then storage capacity is maximized, but program disturbance and lateral charge diffusion increase, worsening error occurrence probability
Solution Approach 1:
Different interleaving patterns are applied to different regions of the memory array based on local interference characteristics. By adapting the data distribution strategy to local conditions, the patent minimizes program disturbance and lateral charge diffusion effects in specific areas while maintaining overall storage capacity through multi-bit memory cells.
Solution Approach 2:
Data is pre-processed using interleaving techniques before being written to memory cells, strategically distributing data to avoid adjacent cells with conflicting states. This preliminary arrangement prevents program disturbance and lateral charge diffusion before they can occur, thereby reducing error occurrence probability while maximizing storage capacity.
3Speed
If data is stored without rearrangement, then write speed is improved, but interference between memory cells increases, worsening error occurrence probability
Solution Approach 1:
Data is segmented into multiple interleaved blocks that can be written in parallel to different memory regions. This segmentation enables high-speed parallel writing while distributing interference effects across multiple blocks, thereby maintaining write speed while reducing error occurrence probability through reduced inter-cell interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes error occurrence and enhances data retention by preventing adjacent memory cells from having conflicting states, thereby improving the reliability of multi-bit data storage in semiconductor memory devices.
Implementation Method 1
The electric charges (or electrons) stored in a floating gate may leak due to various fail mechanisms such as thermionic emission
Implementation Method 2
The electric charges (or electrons) stored in a floating gate may leak due to various fail mechanisms such as charge diffusion
Data Source
AI summary
Provided are a semiconductor memory device and a data processing method thereof. The semiconductor memory device includes a nonvolatile memory and a memory controller. The nonvolatile memory stores data a plurality of memory cells. The memory controller rearranges data by various operations such as a modulation code operation and processes the data according to an ECC operation to reduce the interference between the memory cells.