Two-Stage Memory Data Layouts for Smaller QLC Write Buffers
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Solution Overview
Problem
Memory systems face challenges with increased complexity and cost due to large write buffer sizes required for quad-level cell (QLC) operations, which are unsustainable for some systems, and existing data layout schemes do not efficiently manage buffer sizes and reading efficiencies.
Innovation Solution
Implementing a two-stage data layout scheme where data is initially written using a little-z layout to a smaller buffer in SLCs, MLCs, or TLCs, and then transferred during idle times to QLCs, reordering to a big-z layout for efficient reading, reducing write buffer size while maintaining reading efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a big-z data layout scheme is used for QLC operations, then reading efficiency is improved, but write buffer size and system complexity increase significantly
Solution Approach 1:
The patent segments the write operation into two distinct phases: a first write operation using little-z layout to initial memory locations, and a second write operation using big-z layout to final memory locations. This segmentation allows the system to use a smaller buffer during the first phase while still achieving efficient reads during the second phase, thereby resolving the contradiction between reading efficiency and buffer size requirements.
Solution Approach 2:
The patent performs preliminary sorting and organization of data during the first write operation using little-z layout before the actual read operation occurs. By preparing the data in advance with a smaller buffer footprint, the system reduces the immediate buffer size requirements while maintaining the capability for efficient subsequent reads when the data is reorganized into big-z layout.
2Productivity
If data is written directly to QLCs using big-z layout, then reading efficiency is optimized, but the write buffer size becomes unsustainable for some memory systems
Solution Approach 1:
The patent divides the write process into two separate write operations: the first write operation stores data in initial memory locations using little-z layout with a smaller buffer, and the second write operation transfers and reorganizes the data to final memory locations using big-z layout. This segmentation enables sustainable buffer usage while preserving read efficiency.
Solution Approach 2:
The patent changes the data layout parameter from little-z to big-z between the first and second write operations. This parameter change allows the system to use a smaller buffer during initial writing while achieving optimized read performance after the layout transformation is complete, making the buffer size sustainable for various memory system configurations.
3Ease of manufacture
If existing data layout schemes are used, then implementation is simple, but buffer size management and reading efficiency are not optimized
Solution Approach 1:
The patent introduces dynamic adaptability by allowing the system to choose between little-z and big-z layout schemes based on operational requirements. The controller dynamically manages the two-stage write process, switching between layout modes as needed, which optimizes both buffer utilization and reading efficiency while maintaining implementation flexibility.
Data Source
AI summary
Methods, systems, and devices for data layout configurations for access operations are described. The memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. The first set of memory cells may be written to as single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs). The memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. The second set of memory cells may be written to as quad-level cells (QLCs). The memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.