Multi-bank Semiconductor Memory Data Line Segmentation
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Solution Overview
Problem
In multi-bank semiconductor memory devices, the long data input/output lines create a large load, limiting data transmission speed and increasing current consumption, even when high power voltage is used to compensate for speed decreases.
Innovation Solution
The device employs a bank set with first to fourth memory banks, horizontal and vertical data lines, bank read amplifiers, read drivers, a high impedance driver, and a global amplifier to manage data transmission using high and low power voltages strategically, minimizing data losses and reducing current consumption in data lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high power voltage is used to compensate for data transmission speed decrease, then data transmission speed is maintained, but current consumption in data lines becomes large
Solution Approach 1:
The patent segments the data transmission path into multiple stages with different voltage levels. Internal data lines use low power voltage for local communication between memory banks, while only the final global data line uses high power voltage for external output. This segmentation reduces overall current consumption while maintaining transmission speed.
Solution Approach 2:
Different parts of the data transmission system operate at different power voltages according to their specific requirements. Internal data lines require only low power voltage for local operations, while the global data line requires high power voltage for external communication. This local quality approach optimizes power usage in each segment.
2Device complexity
If the same global data line is used for all memory banks, then device structure is simplified, but data transmission speed is limited due to large load
Solution Approach 1:
The patent segments the single global data line into multiple local data lines connecting different memory banks. Each memory bank has its own local data line for internal communication, and these local lines converge into the global data line only at the output stage. This segmentation reduces the load on each individual line while maintaining structural organization.
Solution Approach 2:
The patent introduces a hierarchical dimension to data line organization, transitioning from a flat single-line structure to a multi-level structure with local and global lines. This dimensional change allows data to be transmitted through shorter local lines before joining the global line, reducing overall transmission distance and load.
Data Source
AI summary
Disclosed herein is a multi-bank type semiconductor memory device which reduces current consumption of data lines. In the multi-bank type semiconductor memory device according to the present invention, the data lines between each memory bank and an input/output buffer are divided into horizontal data lines and vertical data lines. In addition, a high impedance driver is provided to drive horizontal local data of the horizontal data line to provide the horizontal local data as vertical local data of the vertical data line. Therefore, in the multi-bank type semiconductor memory device according to the present invention, even when the horizontal local data and the vertical local data are controlled at a low power voltage, degradation in overall operating speed hardly occurs. In addition, in the multi-bank type semiconductor memory device according to the present invention, current consumption in the data lines is significantly reduced.