Segmented Memory Data Lines for Higher Bandwidth Without Dummy Columns
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Solution Overview
Problem
As technology nodes shrink, DRAM devices face challenges in maintaining high memory cell density while achieving increased memory bandwidth without introducing physical gaps and dummy columns, which waste chip area and increase costs.
Innovation Solution
Implement a segmented data line structure where data lines are divided into multiple line segments, with each segment being multiplexed outside the sense amplifier region to maintain high memory cell density and increase I/O bandwidth without physical gaps or dummy columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data lines are segmented into multiple line segments, then memory bandwidth is increased, but device complexity increases
Solution Approach 1:
The data lines are divided into multiple separate line segments (first line segment, second line segment, third line segment) instead of using a single continuous data line. This segmentation allows parallel data transmission through multiple paths, increasing memory bandwidth while managing complexity through systematic organization of the segments.
Solution Approach 2:
The patent introduces a temporal dimension to data transmission by enabling different bitlines to be coupled to different line segments at different times through the column selection circuit. This time-multiplexing approach increases effective bandwidth without proportionally increasing physical structure complexity.
2Productivity
If data lines are segmented into multiple line segments, then I/O bandwidth is increased, but manufacturing complexity increases
Solution Approach 1:
The data lines are divided into multiple separate line segments (first line segment, second line segment, third line segment) instead of using a single continuous data line. This segmentation allows parallel data transmission through multiple paths, increasing memory bandwidth while managing complexity through systematic organization of the segments.
Solution Approach 2:
Multiple bitlines share common line segments through the column selection circuit, which selectively couples different bitlines to different line segments. This multi-functionality reduces the total number of independent data lines needed, simplifying manufacturing while maintaining high I/O bandwidth.
3Productivity
If segmented data line structure is implemented, then memory bandwidth increases, but chip area utilization decreases
Solution Approach 1:
Multiple bitlines share common line segments through the column selection circuit, which selectively couples different bitlines to different line segments. This multi-functionality reduces the total number of independent data lines needed, simplifying manufacturing while maintaining high I/O bandwidth.
Solution Approach 2:
The column selection circuit dynamically couples different bitlines to different line segments based on operational requirements. This dynamic reconfiguration allows the same physical infrastructure to support higher bandwidth operations without requiring proportional increases in chip area.
Data Source
AI summary
A memory device includes a plurality of sets of bitlines, a set of data lines and a column selection circuit. Each data line is segmented into line segments separated from each other. A first data line includes a first line segment and a second line segment adjacent to each other. A second data line includes a first line segment. The column selection circuit is configured to selectively a first bitline in a first set of bitlines and a first bitline in a second set of bitlines to the first line segment and the second line segment of the first data line, respectively, and to selectively couple a second bitline in the first set of bitlines and a second bitline in the second set of bitlines to the first line segment of the second data line.