Semiconductor Memory Data Line Select Transistor Area Penalty
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving a smaller pitch structure for data lines without incurring significant area penalties, particularly due to alignment deviations in photolithography and the need for select transistors between local and global data lines, which complicates the formation of plugs and increases manufacturing costs.
Innovation Solution
The semiconductor memory device design includes local and global data lines with select transistors that utilize multiple select lines to independently control connections between local data lines and a global data line, minimizing area penalties by optimizing the placement and width of select lines relative to gate electrodes, allowing for tighter pitch and reduced alignment errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the pitch of data lines is reduced to achieve higher density, then the chip area is reduced, but alignment deviations cause short defects between adjacent wirings
Solution Approach 1:
The data line connection structure is segmented into multiple independent plugs rather than a single large plug. Each plug connects to a specific wiring, creating isolated connection points that prevent short defects even when pitch is reduced. The segmentation allows each plug to be smaller than the pitch interval, eliminating the shorting problem while maintaining total connectivity.
Solution Approach 2:
The invention transitions from a single-plane plug arrangement to a multi-layer structure where plugs are distributed across different vertical levels. By stacking plugs in multiple layers, the horizontal pitch can be reduced without causing shorts, as the vertical separation provides additional spacing. This dimensional change allows higher density while maintaining reliability.
2Adaptability or versatility
If select transistors are added between local and global data lines to enable independent control, then the connectivity and control capability are improved, but the area penalty increases
Solution Approach 1:
The invention merges the select transistor gate electrode with the control electrode structure, eliminating the need for separate select transistor components. By combining these functions into a single integrated electrode, the area penalty is significantly reduced while maintaining the independent control capability between local and global data lines.
Solution Approach 2:
The control electrode serves multiple functions simultaneously: it acts as both the word line for memory cell selection and the gate electrode for select transistor operation. This multi-functionality eliminates redundant structures and reduces the overall area required for achieving independent control of data line connections.
3Reliability
If the plug diameter is increased to ensure reliable connection, then the connection reliability is improved, but the pitch interval must be increased, reducing density
Solution Approach 1:
The connection structure is segmented into multiple smaller plugs distributed across the wiring cross-section, rather than relying on a single large plug. Each small plug provides a reliable connection point, and the collective arrangement ensures overall connection reliability while maintaining a compact pitch interval that enables higher density.
Data Source
AI summary
The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.