Memory Data Loop-Back for Low-Power Phase Drift Compensation
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Solution Overview
Problem
Existing memory systems face challenges in managing chip-to-chip phase drift due to temperature and voltage variations, leading to increased power consumption and performance penalties, particularly in mobile applications, as conventional PLL/DLL circuits are power-hungry and difficult to disable.
Innovation Solution
A mesochronous signaling system with a memory controller-based phase compensation mechanism, omitting memory-side PLL/DLL, uses a data-rate clock signal distribution to compensate for phase drift, enabling rapid transitions between clocked and clock-stopped modes with minimal performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLL/DLL circuits are used to compensate for phase drift, then phase alignment between chips is maintained, but power consumption increases significantly during idle periods
Solution Approach 1:
The patent implements periodic calibration of phase offset values at predetermined intervals rather than continuous operation of PLL/DLL circuits. The memory controller periodically updates compensation values based on calibration data, allowing the system to maintain phase alignment while consuming minimal power during idle periods between calibration events.
Solution Approach 2:
The patent pre-calculates and stores compensation values for different temperature and voltage conditions during manufacturing or initial setup. These lookup tables are prepared in advance, allowing the system to quickly apply appropriate compensation without requiring continuous active calibration, thus reducing power consumption while maintaining reliability.
2Reliability
If PLL/DLL circuits are used to maintain phase lock, then synchronous communication is achieved, but lock recovery time increases when waking from power-saving state
Solution Approach 1:
The patent pre-computes and stores compensation values for various operating conditions during manufacturing or initial calibration. When the system wakes from a power-saving state, it can immediately apply the appropriate pre-computed compensation value based on current temperature and voltage sensors, avoiding the time-consuming process of re-establishing phase lock through continuous PLL/DLL operation.
Solution Approach 2:
The patent replaces the continuous feedback control mechanism of PLL/DLL circuits with a lookup table-based compensation system. Instead of mechanically/ electrically adjusting phases through locked-loop circuits, the system uses pre-computed data and sensor readings to directly determine compensation values, significantly reducing wake-up time while maintaining synchronous communication reliability.
3Reliability
If source-synchronous timing signals are transmitted to control data sampling, then phase drift is compensated, but additional pins and signal lines are required increasing device complexity
Solution Approach 1:
The patent uses existing data signal lines to carry both data and timing calibration information. The same physical channels that transmit data between memory controller and memory devices are also used to convey phase calibration data and compensation information, eliminating the need for separate dedicated timing signal lines and reducing overall device complexity.
Solution Approach 2:
The patent introduces a data loopback mode where data signals are routed back through the memory device to the controller, serving as an intermediary mechanism for calibration. This loopback path allows the system to measure and compensate for phase drift using existing signal paths without requiring additional dedicated timing lines, thus maintaining reliability while reducing complexity.
4Ease of operation
If clock buffering circuitry is provided within each chip to fan-out clock signals, then timing is distributed to various circuits, but chip-to-chip phase offset drift increases with temperature and voltage
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller periodically calibrates the phase offset by transmitting calibration patterns through the memory device and measuring the actual phase difference. Based on this feedback, the controller adjusts compensation values to counteract drift caused by temperature and voltage variations, maintaining reliable timing despite environmental changes while preserving the benefits of distributed clock buffering.
Data Source
AI summary
A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.