Multi-Level Non-Volatile Memory Data Mapping for Error Uniformity
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Solution Overview
Problem
Non-volatile memory devices, such as flash memory, face inefficiencies due to non-uniform error distributions across different types of pages, particularly between most significant bits (MSB) and least significant bits (LSB) pages, leading to performance bottlenecks and reduced data reliability.
Innovation Solution
Implementing a system that maps data sectors to non-volatile memory in a way that combines bits of different significance across pages, using techniques like Gray code mapping and selecting nominal threshold voltages to ensure statistically similar bit error rates for all bit positions, thereby creating a more uniform error distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data is mapped uniformly across all pages, then device complexity is reduced, but error distribution becomes non-uniform leading to performance bottlenecks
Solution Approach 1:
The patent applies local quality by differentiating the treatment of different bit positions within data sectors. Specifically, least significant bits (LSBs) and most significant bits (MSBs) are mapped to different pages based on their error characteristics. LSBs are mapped to pages with lower error rates while MSBs are mapped to pages with higher error rates, creating a locally optimized error distribution that improves overall reliability without excessive complexity.
2Ease of operation
If all bit positions are treated equally, then ease of operation is improved, but data reliability deteriorates due to non-uniform error rates across pages
Solution Approach 1:
The patent changes the mapping parameter from a uniform approach to a bit-position-dependent approach. By identifying whether bits are LSBs or MSBs and applying different page mapping strategies for each type, the system achieves statistically similar error rates across all bit positions. This parameter differentiation maintains ease of operation through systematic rules while dramatically improving reliability.
3Productivity
If data sectors are mapped to pages without considering bit significance, then productivity is maintained, but performance bottlenecks occur due to non-uniform error distribution
Solution Approach 1:
The patent implements local quality optimization by assigning different pages to different bit significance groups. LSBs are directed to pages with characteristics suitable for lower error rates, while MSBs are assigned to pages that can tolerate or correct higher error rates. This localized optimization eliminates performance bottlenecks caused by uniformly high error rates while maintaining high productivity through efficient parallel access to different page types.
Data Source
AI summary
An apparatus includes, in at least one aspect, a memory interface configured to connect with a plurality of multi-level memory cells and a circuitry coupled with the memory interface. The plurality of multi-level memory cells include a first page and a second page. The first page is associated with bits of a first significance. The second page is associated with bits of a second significance. The circuitry is configured to map a first portion of an encoded data sector to the first page and map a second portion of the encoded data sector to the second page. The first portion excludes the second portion and the second portion excludes the first portion such that each of the first page and the second page contains different data from the encoded data sector.