Semiconductor Memory Data Output Timing Control with DLL
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Solution Overview
Problem
Conventional semiconductor memory devices face difficulties in maintaining accurate data output timing at high frequencies when the delay locked loop is disabled, leading to reduced operation reliability and increased power consumption.
Innovation Solution
A semiconductor memory device with a data output control unit that generates an output enable signal and determines data output timing based on CAS latency, using a delay locked clock whose phase is controlled by an operation controller, allowing for compensation of system clock delays both when the delay locked loop is enabled and disabled.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the delay locked loop is disabled to reduce power consumption, then power consumption is reduced, but data output timing accuracy deteriorates at high frequencies
Solution Approach 1:
The patent applies dynamics by making the delay compensation mechanism adaptive rather than static. The operation controller dynamically adjusts the delay amount based on real-time detection of clock signal phases. When the DLL is disabled, the system automatically compensates by detecting phase differences and adjusting delays accordingly, allowing the data output timing to remain accurate across varying frequencies without requiring the DLL to be continuously enabled.
Solution Approach 2:
The system implements self-service through automatic phase detection and delay adjustment mechanisms. The operation controller autonomously monitors the clock signal phases and adjusts the delay amounts without external intervention or requiring the DLL to remain active. This self-adjusting capability allows the system to maintain timing accuracy while operating in low-power mode with the DLL disabled.
2Reliability
If the delay locked loop is enabled to maintain data output timing accuracy, then data output timing accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by using periodic phase detection and intermittent delay adjustment. Instead of continuously operating the DLL, the system periodically detects clock signal phases and makes necessary delay adjustments only when needed. This periodic operation allows the DLL to be disabled during normal operation, reducing power consumption while maintaining timing accuracy through targeted interventions.
Solution Approach 2:
The system applies parameter changes by dynamically modifying delay amounts based on detected phase differences. Rather than maintaining a fixed delay configuration or continuously running the DLL, the operation controller adjusts delay parameters only when phase misalignment is detected, changing the system state from a high-power continuous correction mode to a low-power adaptive correction mode.
3Productivity
If the system operates at high frequency to increase data input/output speed, then productivity is improved, but data output timing synchronization deteriorates when DLL is disabled
Solution Approach 1:
The patent implements feedback mechanisms by continuously monitoring clock signal phases and using this information to adjust delay amounts. The operation controller detects phase differences between clock signals and feeds this information back to the delay control logic, which then adjusts the delay to maintain proper timing synchronization. This closed-loop feedback enables high-frequency operation with accurate timing even when the DLL is disabled.
Solution Approach 2:
The system applies preliminary action by performing phase detection and delay adjustment in advance of data output operations. The operation controller proactively monitors clock phases and makes necessary delay corrections before timing-critical operations occur, ensuring that data output timing remains synchronized with the clock signals even at high frequencies without requiring continuous DLL operation.
Data Source
AI summary
A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform a delay locking operation on an internal clock to output delay locked clock, and a data output control unit configured to determine a data output timing, according to whether the delay locked loop is enabled or disabled, in response to a read command.