Memory Device Data Paths for Array Consolidation
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Solution Overview
Problem
Conventional memory device layouts require additional space and increase time delays due to the need for doubled master data lines for array/port consolidation and swapping, which affects performance and size efficiency.
Innovation Solution
A memory device layout where each master data line is positioned between a memory array and a port pad, with local data lines crossing multiple arrays and connecting to master lines, allowing data access through either port pad without increasing space or time delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If doubled master data lines are used for array/port consolidation and swapping, then array/port consolidation and swapping capability is improved, but device area increases
Solution Approach 1:
Each master data line is designed to serve multiple memory arrays by being electrically connectable to different local data line pairs through switches, allowing a single master data line to perform multiple functions across different arrays and ports, thereby eliminating the need for doubled master data lines
Solution Approach 2:
The patent introduces switches that can dynamically reconfigure the electrical connections between master data lines and local data line pairs, allowing the data paths to be dynamically adjusted for different array/port combinations without requiring physical duplication of master data lines
2Adaptability or versatility
If doubled master data lines are used for array/port consolidation and swapping, then array/port consolidation and swapping capability is improved, but time delay increases
Solution Approach 1:
By making each master data line electrically connectable to multiple local data line pairs through switches, the patent eliminates the need for doubled master data lines, thereby preventing the time delay that would result from signal transmission through longer doubled paths
Solution Approach 2:
The dynamic switching capability allows the system to select optimal data paths with minimal delay by configuring switches to connect master data lines to the appropriate local data line pairs based on the current access requirements, avoiding fixed long paths
3Adaptability or versatility
If local data lines cross multiple arrays, then array/port consolidation and swapping is enabled, but data path complexity increases
Solution Approach 1:
The patent segments the data path into modular components: master data lines connecting ports to memory arrays, local data line pairs connecting within arrays, and switches providing selective connections. This segmentation allows complex array/port consolidation functionality to be achieved through simple, standardized modules rather than complex integrated paths
Data Source
AI summary
Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads including a plurality of contacts; a plurality of memory arrays; and a plurality of master data lines. Each of the master data lines extends in a space between one of the port pads and a respective one of the memory arrays. Each of the master data lines is electrically connectable to the contacts of a respective one of the port pads. The apparatus further includes a plurality of local data lines, each of which extends over a respective one of the memory arrays. Each of the local data lines is electrically connectable to a respective one of the master data lines. At least one of the local data lines extends over at least two of the memory arrays. This configuration allows memory array consolidation and/or swapping without increasing die space for additional routing and adversely affecting performance of the apparatus.