Memory Subsystem Data Pattern Checker for Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory subsystems face challenges in reducing power consumption, particularly due to the need to transfer large amounts of data, with conventional methods like voltage scaling limited by performance degradations.
Innovation Solution
Implementing a system where repeated data patterns are identified and stored in buffers, allowing only the corresponding address to be transferred on a separate bus, reducing data traffic and power consumption by suppressing the transfer of the data pattern itself.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If voltage scaling is used to reduce power consumption, then power consumption decreases, but performance degrades due to limitations imposed by refresh operations and memory peripheral I/O circuitry
Solution Approach 1:
The patent extracts only the essential information (address) from the complete data transfer, suppressing the transfer of full data patterns when they are repeated. This reduces the volume of data transmitted over the bus, thereby reducing power consumption without requiring voltage scaling that would degrade performance.
Solution Approach 2:
The patent changes the parameter being transferred from full data patterns to compressed address representations. This parameter transformation reduces the amount of data transmission while maintaining the ability to retrieve complete data, achieving power savings without performance degradation.
2Reliability
If full data patterns are transferred on the data bus, then complete data is available at the destination, but power consumption increases due to large data traffic
Solution Approach 1:
The patent creates a compressed copy (address) of the full data pattern instead of transferring the complete data. The receiving end can retrieve the full data from storage using this address copy, achieving the same result with significantly reduced power consumption.
Solution Approach 2:
The system performs preliminary action by storing complete data patterns in advance at both transmitter and receiver ends. When a pattern is detected, the pre-stored data can be referenced without retransmission, reducing power consumption while maintaining data completeness.
Data Source
AI summary
Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.