Memory Controller Data Placement for Flash Bit Error Reduction
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Solution Overview
Problem
Flash memory systems face challenges in maintaining data reliability and endurance due to high bit error rates and inter-cell interference, particularly in multi-level cell modes, where data fatigue and incorrect read values occur, affecting the lifespan and reliability of memory cells.
Innovation Solution
A memory controller system that includes a compression unit, error mitigating code unit, and write control unit, which performs data translation and error correction coding based on device characteristics to optimize data placement across physical sectors, reducing bit error rates and enhancing memory endurance by selecting appropriate sectors for writing data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written into blocks with low bit error rate, then data reliability is improved, but blocks with high bit error rate cannot be utilized effectively
Solution Approach 1:
The patent applies local quality by dividing the memory device into multiple blocks with different characteristics and assigning data with different rewriting frequencies to appropriate blocks. High reliability data goes to low bit error rate blocks, while low reliability data goes to high bit error rate blocks, optimizing overall system performance by matching data characteristics to block characteristics.
Solution Approach 2:
The patent changes the parameter of block selection based on bit error rate characteristics. By monitoring and categorizing blocks according to their bit error rates and dynamically selecting appropriate blocks for different data types, the system adapts to varying block conditions and maintains optimal data reliability.
2Reliability
If high rewriting frequency data is stored in low bit error rate blocks, then data integrity is maintained, but block wear is accelerated
Solution Approach 1:
The patent applies local quality by matching data rewriting frequency characteristics to block endurance characteristics. Frequently rewritten data is stored in blocks with higher endurance capacity, while less frequently rewritten data is stored in more sensitive blocks, thereby distributing wear evenly and extending overall system lifespan.
Solution Approach 2:
The patent implements a wear-leveling strategy that effectively creates virtual copies of storage capacity across different block types. By redirecting write operations to appropriate blocks based on their characteristics, the system extends the operational life of the memory device without compromising data integrity.
3Reliability
If error correction coding is applied to all data, then bit error rate is reduced, but processing overhead increases
Solution Approach 1:
The patent applies partial action by selectively applying error correction coding only to data that requires it, based on the block's bit error rate characteristics. Low bit error rate blocks receive full error correction treatment, while high bit error rate blocks use alternative strategies, thereby reducing overall processing overhead while maintaining necessary reliability.
Solution Approach 2:
The patent changes the error correction parameter based on block characteristics. By adjusting the level of error correction applied according to the measured bit error rate of each block, the system optimizes the balance between reliability and processing efficiency, applying stronger correction only where needed.
Data Source
AI summary
According to one embodiment, a control unit determines a first physical sector in which first data is to be written among a plurality of physical sectors based on first information that is based on a result of the first data translation and the device characteristics of the plurality of physical sectors. A write unit writes data for which a first data translation is performed into the first physical sector of a nonvolatile memory.