Memory Data Placement by Access Frequency

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Solution Overview

Problem

Current memory management systems inefficiently utilize memory space by not considering the relative frequency of data unit access and memory latency, leading to suboptimal placement of data units, resulting in increased latency and overhead due to unnecessary data copies.

Innovation Solution

A method that determines the usage frequency of data units and moves them to memory locations based on their corresponding latency classes, prioritizing high-frequency data in low-latency locations and low-frequency data in high-latency locations, eliminating the need for duplicate data copies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data units are placed in faster memory portions, then access speed is improved, but memory space utilization becomes inefficient when considering usage frequency

Engineering Contradiction:
Improvememory access speedVSAvoidmemory space utilization efficiency
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent applies local quality by differentiating memory locations based on their access characteristics. Frequently accessed data units are placed in faster memory portions (lower latency locations), while less frequently accessed data units are placed in slower memory portions. This creates a non-uniform memory organization where different regions have different access speeds tailored to the specific access patterns of the data they store, thereby optimizing both speed and space utilization efficiency.

Inventive Principle:
Principle #3Local quality

2Speed

If data is stored in hierarchical memory levels with copies, then access speed is improved, but memory overhead and complexity increase

Engineering Contradiction:
Improvedata access speedVSAvoidmemory structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements preliminary action by proactively monitoring usage frequency of data units and preemptively relocating them to optimal memory locations before access occurs. The memory controller continuously tracks access patterns and performs data movement operations in advance, so that when a data unit is needed, it is already positioned in the fastest available memory location. This eliminates the need for complex hierarchical copying mechanisms while maintaining fast access performance.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If uniform memory access is implemented, then simplicity is maintained, but performance is reduced due to ignoring latency variations

Engineering Contradiction:
Improvememory access simplicityVSAvoidmemory access latency
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the memory allocation strategy adaptive rather than static. The memory controller dynamically adjusts the placement of data units based on real-time usage frequency monitoring. As access patterns change, the system automatically repositions data units to optimize performance. This dynamic approach maintains operational simplicity from the user perspective while internally adapting to latency variations and access patterns to minimize access time.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8255628B2Structure for multi-level memory architecture with data prioritization
Publication Date: 2012.08.28 LENOVO GLOBAL TECHNOLOGIES SWITZERLAND INTERNATIONAL GMBH
  • US8255628B2 patent drawing
  • US8255628B2 patent drawing
  • US8255628B2 patent drawing

AI summary

A design structure for controlling computer-readable memory includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location, different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit.