Nonvolatile Memory Data Preservation via Internal Register Caching

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Solution Overview

Problem

Nonvolatile storage memory components, such as solid state drives, face data loss due to programming failures during write operations, especially when external volatile memory caches or Exclusive-OR data recovery processes are absent, leading to inefficiencies and performance issues.

Innovation Solution

Implementing an internal data preservation and recovery process within the memory controller that transfers data to a backup register before releasing the write register, allowing for quick recovery of data in case of programming failures, independent of external caches or time-consuming Exclusive-OR processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is cached in internal latches or registers during programming interval, then write process time is reduced, but data loss occurs upon programming failure

Engineering Contradiction:

Improvewrite process timeVSAvoiddata loss

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by caching the next page of data in internal latches or registers during the programming interval of the current page. This allows the write process to overlap operations and reduce total write time, while the cached data serves as a preliminary preparation for the next programming operation.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies copying by maintaining cached copies of data pages in internal latches or registers. When a programming failure occurs, the cached copy can be re-programmed without requiring external volatile memory or time-consuming read-retry operations, thus resolving the data loss issue while maintaining improved write performance.

Inventive Principle:

Principle #26Copying

2Reliability

If external volatile memory cache is used to preserve data, then data loss is prevented, but device complexity and access time increase

Engineering Contradiction:

Improvedata preservationVSAvoidmemory architecture

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies multi-functionality by using the internal latches or registers that already exist in the memory component for dual purposes: (1) as part of the normal write operation pipeline to cache next pages during programming intervals, and (2) as a safety mechanism to preserve data upon programming failures. This eliminates the need for separate external volatile memory caches while maintaining data preservation capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If Exclusive-OR process is applied for data recovery, then data loss is recovered, but processing time increases

Engineering Contradiction:

Improvedata recoveryVSAvoidrecovery time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-caching data pages in internal latches or registers during the programming interval of previous pages. This preliminary caching ensures that recovery data is already available in fast internal memory, eliminating the need for time-consuming read-retry operations and Exclusive-OR processing of data from the bitcell array.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10268578B1Data preservation and recovery in a memory component

Publication Date: 2019.04.23 SK HYNIX NAND PRODUCT SOLUTIONS CORP

AI summary

In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.