Memory Sub-System Data Recovery via Selective Error Correction

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Solution Overview

Problem

Existing memory sub-systems face challenges in efficiently handling and recovering data after an unsuccessful error correction operation, which can lead to data errors and reduced system performance.

Innovation Solution

The memory sub-system implements a method to recover data by performing a recovery operation on data associated with an unsuccessful error correction operation and relocating it to a new memory cell, thereby minimizing delays in incoming read/program requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is stored on malfunctioning memory cells, then storage capacity is maintained, but data reliability deteriorates

Engineering Contradiction:
Improvedata reliabilityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts problematic data from malfunctioning memory cells through error correction operations. When errors are detected during read operations, the system identifies and separates corrupted data from valid data, relocating only the erroneous portions to functional memory cells while preserving overall storage capacity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary error correction operations before data is permanently lost. By continuously monitoring and correcting errors in real-time during read operations, the system prevents data degradation from escalating to complete data loss, maintaining reliability proactively.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If error correction operations are performed on all data, then data reliability is improved, but processing time increases

Engineering Contradiction:
Improvedata accuracyVSAvoidprocessing delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies error correction selectively rather than uniformly to all data. Error correction operations are targeted specifically at data blocks that exhibit error patterns or are stored in memory cells with known degradation, reducing unnecessary processing of already-healthy data while maintaining high reliability where needed.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent performs partial error correction by focusing computational resources on the most vulnerable or error-prone data portions. Rather than exhaustively correcting every possible error in the entire storage system, the system applies correction to the minimum necessary subsets of data to maintain acceptable reliability thresholds.

Inventive Principle:
Principle #16Partial or excessive action

3Manufacturing precision

If data is relocated from malfunctioning memory cells, then data retention accuracy is improved, but operational complexity increases

Engineering Contradiction:
Improvedata retention accuracyVSAvoidsystem complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements a universal error correction and data relocation framework that handles multiple types of memory errors and degradation patterns through a single integrated system. The same error detection, correction, and relocation mechanisms work across different memory cell types and failure modes, reducing the need for specialized handling procedures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent enables the memory system to automatically detect, correct, and relocate erroneous data without external intervention. The error correction operations are performed autonomously by the memory controller, which independently identifies problematic data and transfers it to functional cells, reducing the operational burden on external systems.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250147686A1Data recovery in memory devices
Publication Date: 2025.05.08 MICRON TECHNOLOGY INC
  • US20250147686A1 patent drawing
  • US20250147686A1 patent drawing
  • US20250147686A1 patent drawing

AI summary

An example system includes a memory device; and a processing device, operatively coupled to the memory device, to perform operations, including: programming a plurality of pages of the memory device; adjusting a program verify voltage associated with the plurality of pages; responsive to determining that a first error rate of a first page of the plurality of pages exceeds a second error rate of a second page of the plurality of pages, performing a recovery operation on the first page to produce recovered data; and storing the recovered data on the memory device.