Solid-State Memory Data Recycling for Low-Latency Error Correction

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Solution Overview

Problem

Data in solid state storage devices decays over time, requiring increased error correction capability, which in turn increases access latency, necessitating advanced systems and methods for maintaining data reliability and reducing latency.

Innovation Solution

The implementation of an iterative data processing system that applies data decoding algorithms to correct errors, with a recycle control circuit determining whether to recycle data based on iteration count and access frequency, using a comparator to adjust thresholds for recycling decisions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If enhanced error correction circuitry is employed to correct additional errors, then data reliability is improved, but access latency increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidaccess latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary data recycling by detecting iteration counts during error correction attempts and proactively recycling data before actual read operations. This preliminary action prepares data in advance, ensuring reliability without incurring latency during actual access operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory system performs self-service by autonomously monitoring its own error correction performance through iteration counts and automatically recycling data that shows signs of degradation. This self-service mechanism maintains reliability without external intervention or additional latency impact on normal operations.

Inventive Principle:
Principle #25Self-service

2Reliability

If data is recycled frequently to maintain reliability, then data decay impact is reduced, but access latency increases due to additional error correction iterations

Engineering Contradiction:
Improvedata integrityVSAvoidaccess latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system changes the parameter being monitored from actual read latency to error correction iteration count. By using iteration count as a proxy indicator of data degradation, the system can make recycling decisions based on error correction performance rather than reacting to latency issues, thereby maintaining reliability without penalizing access speed.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system implements feedback by continuously monitoring error correction iteration counts and using this information to trigger data recycling. This feedback loop enables the system to maintain data integrity by responding to actual error correction needs rather than using fixed or overly conservative recycling thresholds that would increase latency.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10437513B2Systems and methods for latency based data recycling in a solid state memory system
Publication Date: 2019.10.08 SEAGATE TECH LLC
  • US10437513B2 patent drawing
  • US10437513B2 patent drawing
  • US10437513B2 patent drawing

AI summary

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.