Memory Data Steering Logic BIST Testing
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Solution Overview
Problem
Current methods for testing memory arrays are inefficient and time-consuming, particularly due to the difficulty in isolating faults in data steering logic, which is not effectively addressed by conventional Built-In Self-Test (BIST) systems that fail to test I/O circuits responsible for data alignment.
Innovation Solution
A method involving a BIST controller that writes and reads test patterns through dedicated comparators connected to each data bus lane of a memory array, verifying data alignment and operation of write and read data steering logic by comparing patterns across all subunits, thereby isolating and testing the data steering logic efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BIST systems are used to test memory arrays, then the memory array itself can be tested, but the data steering logic in the I/O circuits is not tested
Solution Approach 1:
The patent segments the testing process into two distinct modes: a first test mode for testing the memory array and a second test mode for testing the data steering logic. This segmentation allows each component to be tested independently with appropriate test patterns, ensuring complete coverage of both the memory array and the previously untested data steering logic.
Solution Approach 2:
The patent implements dynamic switching between two test modes through a mode signal. The test controller can transition between the first test mode (testing memory array) and the second test mode (testing data steering logic) by changing the mode signal state. This dynamic capability enables versatile testing of different components within the same system.
2Reliability
If functional testing is used to test memory arrays, then the memory can be tested, but the test process is time consuming and inefficient
Solution Approach 1:
The patent applies preliminary action by pre-configuring specific test patterns in the test controller before initiating the testing process. The test patterns are prepared in advance and automatically applied to the memory array and data steering logic, eliminating the need for time-consuming functional testing procedures and reducing overall test time.
3Reliability
If conventional testing methods are used, then testing can be performed, but fault isolation in data steering logic is difficult
Solution Approach 1:
The patent extracts the data steering logic testing from the general memory testing process by implementing a dedicated second test mode. In this mode, the mode signal is set to specifically activate testing of the data steering logic while the memory array testing is suspended. This extraction allows faults in the data steering logic to be isolated and detected independently from memory faults.
Solution Approach 2:
The patent introduces a mode signal as an intermediary that controls the switching between different test modes. This mode signal acts as a mediator that directs the test controller to appropriately configure the testing process based on whether the first or second test mode is active, enabling clear fault isolation between memory array and data steering logic.
Data Source
AI summary
Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.