Semiconductor Memory Device Data Strobe Cycle Extension
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Single data rate (SDR) semiconductor memory devices experience increased power consumption as the cycle time of the data strobe signal is reduced, necessitating a solution to extend the cycle time of the data strobe signal relative to the clock signal to minimize power consumption.
Innovation Solution
The semiconductor memory device incorporates a data strobe unit that outputs a read data strobe signal with a cycle time n times (n is an integer equal to or more than 2) that of the internal clock signal, allowing for reduced power consumption by synchronizing data output with the clock signal while maintaining effective data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the cycle time of the data strobe signal is reduced to increase data transfer speed, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the cycle time of the data strobe signal variable relative to the clock signal. Specifically, the data strobe signal is configured to have a cycle time that is n times (where n is an integer equal to or more than 2) the cycle time of the internal clock signal, allowing the system to dynamically adjust the strobe frequency to reduce power consumption while maintaining effective data transfer through synchronized timing.
Solution Approach 2:
The patent changes the temporal parameter of the data strobe signal by extending its cycle time to be n times that of the internal clock signal. This parameter change directly addresses the power consumption issue by reducing the switching frequency of the strobe signal, thereby reducing dynamic power consumption while maintaining data integrity through proper synchronization.
2Use of energy by moving object
If the cycle time of the data strobe signal is increased to reduce power consumption, then power consumption is reduced, but data transfer efficiency decreases
Solution Approach 1:
The patent uses the internal clock signal as an intermediary to coordinate between the data strobe signal and the data output unit. The read data strobe unit generates the strobe signal based on the internal clock signal, and the data output unit synchronizes data output with the same internal clock signal, ensuring that data transfer remains efficient despite the extended strobe cycle time.
Solution Approach 2:
The patent employs periodic action by maintaining the synchronized timing relationship between the data strobe signal and the internal clock signal. Even though the strobe cycle time is extended, the periodic synchronization ensures that data is transferred at the appropriate moments, maintaining transfer efficiency while reducing overall power consumption through the longer period.
3Use of energy by moving object
If the data strobe signal cycle time is made larger than the clock signal cycle time, then power consumption is reduced, but signal synchronization complexity increases
Solution Approach 1:
The patent applies universality by using the internal clock signal as a common reference for both the data strobe signal generation and the data output timing. This multi-functional use of the same clock signal simplifies the synchronization mechanism, as both operations derive their timing from the same source, reducing the complexity that would otherwise arise from coordinating multiple independent timing signals.
Data Source
AI summary
A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.