Semiconductor Memory Data Transfer Line Defect Detection
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Solution Overview
Problem
Detecting defects in data transfer lines within semiconductor memory devices is challenging due to the complexity of internal circuits and the difficulty in distinguishing defects in the cell core from defects in data transfer lines, especially in high-speed devices, which can delay product development.
Innovation Solution
A semiconductor memory device apparatus that includes a data transfer unit, a data transfer controller, a test mode controller, and temporary data storage units to detect defects between data pins and local/global I/O lines by preventing activation of specific signals during a test mode, allowing for the monitoring of data transfer and storage of write data to identify defects independently of cell core issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If normal read operation is performed to detect data transfer line defects, then data transfer line defects can be detected, but cell core defects cause false positives and complicate defect analysis
Solution Approach 1:
The patent segments the memory system into two independent test paths: one for cell core testing and another for data transfer line testing. By separating these functions and using different test modes, the system can isolate defects to specific components without interference from other parts, thereby improving detection accuracy and reducing analysis complexity.
Solution Approach 2:
The patent introduces temporary data storage units as intermediaries between the cell core and data transfer lines. These intermediaries allow write data to be stored and later read back, enabling independent testing of data transfer lines without requiring functional cell cores. This mediator approach decouples the testing of different components.
2Productivity
If high-speed operation is implemented to increase data processing capability, then productivity increases, but defect detection time increases and delays product development
Solution Approach 1:
The patent performs preliminary actions by storing write data in temporary data storage units during normal operations. This preliminary storage of data enables subsequent rapid defect detection without requiring time-consuming re-writing or re-generation of test data, thus reducing overall defect detection time while maintaining high-speed operation.
3Measurement precision
If temporary data storage is used to store write data, then data transfer line defects can be detected independently of cell core defects, but device complexity increases
Solution Approach 1:
The temporary data storage units serve multiple functions: they act as buffers during normal read/write operations, serve as test data sources for data transfer line testing, and provide isolation between cell core and data transfer line testing. This multi-functionality reduces the need for separate dedicated test structures, thereby limiting the increase in device complexity.
Data Source
AI summary
An apparatus for detecting a defect of a data transfer line in a semiconductor memory device, including a data transfer unit for transferring data between a local I/O line and a global I/O line; a data transfer controller for controlling the data transfer unit by generating a read signal, a write signal, and a local I/O line reset signal; a test mode controller for preventing an activation of the read signal, a column select signal and the local I/O line reset signal based on a test mode signal; a first temporary data storage for storing data of the global I/O line; and a second temporary data storage for storing data of the local I/O line.