Memory Data-Width Translators for Dynamic Bandwidth Expansion
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Solution Overview
Problem
Integrated circuit memory devices, such as DRAM, face challenges in increasing bandwidth and cell density to match the rapid advancements in processor bandwidth, potentially leading to reduced annual increases in memory cell density, necessitating memory system topologies with high bandwidth capabilities.
Innovation Solution
The implementation of dynamic point-to-point (DPP) technology using variable-width memory modules with data-width translators that adapt fixed-width memory dies, allowing for capacity expansion while maintaining full memory system bandwidth, and the use of data-mask signals to divide physical address locations into temporal subsets, effectively increasing addressable locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory devices are used, then manufacturing and operating simplicity is maintained, but bandwidth and cell density cannot keep pace with processor requirements
Solution Approach 1:
The memory system is segmented into multiple memory modules, each with its own data-mask translator, allowing independent operation and capacity expansion. Each module can be configured with different data widths (1-bit, 2-bit, 4-bit) to match processor requirements while maintaining full bandwidth utilization.
Solution Approach 2:
The memory modules implement dynamic point-to-point (DPP) technology with configurable data widths that can be dynamically adjusted. The data-mask translator dynamically masks subsets of data bits based on configuration signals, enabling the system to adapt bandwidth and capacity to match varying processor requirements without physical reconfiguration.
2Productivity
If memory cell density is increased to match processor bandwidth, then bandwidth capability improves, but operating time and reliability may be compromised
Solution Approach 1:
Instead of increasing memory cell density in the spatial dimension (which compromises reliability), the invention expands capacity in the temporal dimension by dividing physical address locations into temporal subsets. This allows the same physical memory cells to serve multiple logical address locations at different times, achieving high bandwidth without increasing cell density.
3Adaptability or versatility
If fixed-width memory dies are used, then manufacturing simplicity is maintained, but capacity expansion and bandwidth matching are limited
Solution Approach 1:
The data-mask translator serves as an intermediary between the fixed-width memory die and the variable-width external interface. It receives configuration signals that determine which subsets of data bits are masked, effectively translating between the fixed internal width and variable external width requirements, enabling capacity expansion without changing the core memory die.
Data Source
AI summary
Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.