Semiconductor Memory Data Window Synchronization

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Solution Overview

Problem

Semiconductor memory devices face issues with data synchronization due to changes in operation temperature or power, leading to phase shifts in data transfer between data processing apparatuses and memory devices, especially at higher transmission frequencies, causing data to be recognized as shifted backward or forward, affecting normal data transfer.

Innovation Solution

A circuit with first and second data input/output units that synchronize data windows with the source clock edge for training and recovery information data, and a semiconductor memory device controller that compares feedback data to adjust phases, ensuring stable data transfer regardless of temperature or power changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data transmission frequency is increased, then data transfer speed is improved, but data synchronization stability deteriorates due to phase shifts caused by temperature or power changes

Engineering Contradiction:
Improvedata transfer speedVSAvoiddata synchronization stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements a training mode that executes before normal data transfer to pre-synchronize the data window with the source clock edge. During this training mode, the system adjusts the data window positioning in advance based on feedback about phase conditions, ensuring that when normal operation resumes, the data window remains properly synchronized even under varying temperature or power conditions. This preliminary synchronization action prevents phase shift issues from affecting data integrity during high-speed transmission.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs a feedback mechanism where the semiconductor memory device transmits feedback information about its internal state and synchronization status back to the controller. The controller uses this feedback to adjust the data window positioning and timing parameters dynamically. This closed-loop feedback system enables continuous adaptation to changing operating conditions, maintaining data synchronization stability even as transmission frequency increases or environmental conditions vary.

Inventive Principle:
Principle #23Feedback

2Adaptability or versatility

If operation temperature or power is changed, then system adaptability is improved, but data phase synchronization deteriorates causing data to be recognized as shifted

Engineering Contradiction:
Improvesystem adaptability to temperature and power changesVSAvoiddata phase synchronization precision
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent implements a dynamic data window adjustment mechanism that can adapt its positioning and timing characteristics in response to changing operating conditions. The data window is not fixed but can dynamically adjust its synchronization point relative to the source clock edge based on feedback about temperature and power variations. This dynamic adaptation allows the system to maintain precise data phase synchronization while being adaptable to environmental changes.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The feedback mechanism enables the system to detect changes in temperature and power conditions through monitoring of timing parameters and phase relationships. The controller receives feedback about synchronization status and adjusts the data window positioning accordingly, creating a self-regulating system that maintains precision despite environmental variations.

Inventive Principle:
Principle #23Feedback

3Reliability

If data window scanning is based on source clock edge, then synchronization is improved, but sensitivity to phase changes increases causing data recognition errors

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidsensitivity to phase changes
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The training mode performs preliminary adjustment of the data window positioning before normal data transfer begins. During this preparatory phase, the system establishes the correct synchronization relationship between the data window and source clock edge, accounting for any phase shifts that may occur due to temperature or power changes. By performing this alignment action in advance, the system reduces sensitivity to subsequent phase changes during actual data transmission.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The feedback mechanism continuously monitors the phase relationship between the data window and source clock edge, allowing the system to detect and compensate for phase changes. When phase shifts occur due to temperature or power variations, the feedback system triggers adjustments to the data window positioning, thereby reducing the harmful effects of phase changes on data recognition accuracy.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8503254B2Semiconductor memory device, semiconductor system including the semiconductor memory device, and method for operating the semiconductor memory device
Publication Date: 2013.08.06 SK HYNIX INC
  • US8503254B2 patent drawing
  • US8503254B2 patent drawing
  • US8503254B2 patent drawing

AI summary

A semiconductor memory device includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge of the data window is synchronized with the edge of the source clock in response to a training output command, and a second data input/output unit configured to receive a recovery information training data, whose data window is scanned based on the edge of the source clock, in response to the training input command, and output a data in a state where an edge of a data window is synchronized with the edge of the source clock in response to the training output command.