Memory Package DCC Training During Unselected Bus Operation

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Solution Overview

Problem

Existing semiconductor memory systems face challenges in efficiently performing Duty Cycle Correction (DCC) without interrupting or delaying other operations, particularly due to variations in duty cycle that lead to high Bit Error Rates (BER) in data communication.

Innovation Solution

Implementing DCC training as a background operation that allows parallel execution with memory access operations by applying a suitable time offset using a DCC circuit, which searches for an appropriate delay from a list of possible offsets, and utilizes binary search to efficiently correct duty cycle without impacting read data throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If DCC training is performed in a selected memory package, then duty cycle correction is achieved, but memory access operations are interrupted or delayed

Engineering Contradiction:

Improveduty cycle correctionVSAvoidmemory access throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The system divides memory packages into selected and unselected groups, allowing DCC training to be performed in unselected packages while memory access operations continue in selected packages. This segmentation enables parallel execution of DCC training and memory access operations, resolving the contradiction between achieving duty cycle correction and maintaining memory access throughput.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

DCC training is performed as a background operation in unselected memory packages before they become selected for memory access operations. This preliminary action ensures that duty cycle correction is completed in advance, so when the memory package is later selected for access operations, the correction is already in place and does not interrupt the access throughput.

Inventive Principle:

Principle #10Preliminary action

2Measurement precision

If DCC training is performed sequentially, then duty cycle correction is accurate, but system performance is degraded

Engineering Contradiction:

Improveduty cycle correction accuracyVSAvoidsystem performance

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The system maintains continuous useful action by performing DCC training in unselected memory packages while simultaneously performing memory access operations in selected packages. This continuous parallel execution eliminates idle time and ensures that both DCC training and memory access operations proceed without interruption, maintaining both accuracy and system performance.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

DCC training is performed as a preliminary background operation in unselected packages, completing the correction process before the packages are needed for memory access. This preliminary action ensures accurate correction is achieved without causing time loss during actual memory operations, as the correction is already complete when access is required.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12609688B2Background duty cycle correction in unselected die

Publication Date: 2026.04.21 SANDISK TECHNOLOGIES LLC

AI summary

An apparatus includes a control circuit in a first memory package. The control circuit is configured to connect to a bus and to receive a Duty Cycle Correction (DCC) training command over the bus. The control circuit is configured to perform a DCC training operation while the first memory package is unselected and while a second memory package connected to the bus is selected to perform a memory access operation.