Semiconductor Memory Debug via Internal Testing Interface
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Solution Overview
Problem
The increasing complexity of semiconductor device designs makes silicon debug processes incomplete due to the need for large data communication, which is time-consuming and often requires direct connections or unavailable chip-level pins, potentially altering the design under test.
Innovation Solution
A debugging system using a testing interface, such as an internal Joint Test Action Group (iJTAG) interface, that communicates test data with semiconductor devices mounted on a circuit board without modifying the FPGA or requiring access to unavailable chip-level pins, utilizing test control circuitry to manage clock signals and communicate data from memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If memory and scan chain dumps are used to obtain large amounts of data for debugging, then debugging information completeness is improved, but testing time increases significantly
Solution Approach 1:
The patent extracts only the necessary debugging information from the semiconductor device through targeted test operations via the test interface, rather than dumping all memory and scan chain data. This selective extraction approach obtains sufficient debugging information while significantly reducing the time required for data communication.
2Reliability
If a direct connection between test device and semiconductor device is established for data communication, then data transmission reliability is improved, but device complexity and pin requirements increase
Solution Approach 1:
The patent utilizes an existing test interface (such as I2C, SPI, or UART) that serves multiple functions including normal device operation and debugging communication. This multi-functional approach eliminates the need for dedicated debug pins and direct connections, reducing device complexity while maintaining reliable data transmission through the shared interface.
3Ease of operation
If FPGA configuration is modified for state observation during debugging, then debugging capability is improved, but design stability deteriorates
Solution Approach 1:
The patent introduces a test control circuit as an intermediary component that interfaces between the test device and the semiconductor device. This intermediary enables debugging operations by controlling test signal generation and data communication without requiring modifications to the FPGA configuration, thereby maintaining design stability while improving debugging capability.
Data Source
AI summary
A semiconductor device comprises a plurality of memory elements, test control circuitry, and a testing interface. The test control circuitry is configure to determine that one or more clock signals associated with the memory elements have been stopped and generate a scan clock signal based on the determination that the one or more clock signals have been stopped. The test control circuitry is further configured to communicate the scan clock signal to the memory elements. The testing interface is configured to communicate test data from the memory elements. In one example, the test data is delimited with start and end marker elements. The semiconductor device is mounted to a circuit board and is communicatively coupled to communication pins of the circuit board.