Memory Address Decoder Failure Detection With Stored Address Comparison
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently detecting failures in address decoders due to high power overhead and area overhead, as well as circuit complexity, when implementing failure detection methods.
Innovation Solution
A semiconductor memory device design that includes a first memory array, an address decoder, a second memory array for storing address information, and a comparison circuit to compare input address information with stored address information, allowing for simple failure detection of the address decoder with low area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection bits are written into memory each time data is written, then failure detection capability is improved, but power consumption increases
Solution Approach 1:
The patent pre-calculates and stores error detection bits in a separate storage location during manufacturing or initialization, rather than calculating them in real-time during write operations. This preliminary action eliminates the need for continuous power-consuming calculations during normal operation while maintaining failure detection capability.
Solution Approach 2:
The patent creates a copy of the address information and stores it in a dedicated storage area alongside the data. This copy is then used for failure detection by comparing it with the original address information, avoiding the need to re-calculate error detection bits during read operations and thus reducing power consumption.
2Reliability
If error detection bits are stored in memory, then failure detection capability is improved, but memory area overhead increases
Solution Approach 1:
The patent segments the memory structure into distinct functional areas: data storage area, separate error detection bit storage area, and address information storage area. This segmentation allows for efficient use of memory resources and enables targeted failure detection without requiring overhead in the entire memory array.
Solution Approach 2:
The patent introduces a separate storage area as an intermediary structure that holds error detection bits and address information independently from the main data storage. This intermediary structure enables failure detection functionality without consuming additional space within the primary data memory, thus minimizing area overhead.
3Reliability
If address decoder failure detection is implemented by inverting input signal bits, then failure detection capability is improved, but circuit complexity increases
Solution Approach 1:
Instead of inverting input signal bits which requires complex logic circuits, the patent creates a copy of the original address information and stores it in a dedicated storage area. The failure detection is then performed by comparing the stored copy with the original address, which simplifies the circuit design while maintaining detection capability.
Solution Approach 2:
The patent introduces a comparison circuit as an intermediary that compares the stored address information with the current address input. This intermediary approach provides a systematic and simplified method for failure detection without requiring complex signal inversion logic, thereby reducing overall circuit complexity.
Data Source
AI summary
The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.