Non-Volatile Memory Decoder Modules for Bipolar Cell Biasing

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Solution Overview

Problem

Existing decoder modules for non-volatile memory, such as MRAM, face challenges in applying both positive and negative voltages to memory cells due to limitations in multiplexor circuits, making it difficult to program and read cells efficiently.

Innovation Solution

Implementing decoder modules with both positive and negative multiplexor circuits to address memory cells that require both polarities, allowing for efficient programming and reading using a shifting scheme that includes coupling buses to decoders within and outside the decoder module boundaries.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional multiplexor circuits are used in decoder modules, then device complexity is reduced, but the ability to apply both positive and negative voltages to memory cells is limited

Engineering Contradiction:
Improveability to apply both positive and negative voltagesVSAvoiddecoder module complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The decoder module is segmented into separate positive multiplexor circuit and negative multiplexor circuit, allowing independent control of positive and negative voltage applications to memory cells. This segmentation enables the system to handle both polarities effectively without interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The decoder module is designed with universal capability to handle both positive and negative voltages through multiple multiplexor circuits. Each multiplexor circuit can selectively apply its respective polarity voltage to selected memory cells, making the decoder module versatile for different programming and reading operations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of operation

If decoder modules are designed with boundaries, then manufacturing precision is improved, but memory cells outside boundaries cannot be accessed efficiently

Engineering Contradiction:
Improvememory cell accessibilityVSAvoiddecoder module boundary definition
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

Adjacent decoder modules are merged through shared bus connections, allowing a decoder module to access memory cells that are physically located in adjacent modules. The positive and negative buses extend beyond module boundaries to connect with neighboring modules, enabling cross-module cell access.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The bus system acts as an intermediary that connects decoder modules to memory cells outside their immediate boundaries. The positive bus and negative bus serve as mediators that transmit control signals and voltages to selected memory cells regardless of which physical module they reside in.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If shifting scheme is implemented to access cells outside decoder module, then memory cell coverage is improved, but device complexity increases

Engineering Contradiction:
Improvememory cell coverageVSAvoidshifting scheme complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The decoder module implements dynamic addressing through shifting schemes that can adaptively select which memory cells to access based on the current operation requirements. The module can shift its active addressing range to cover cells in adjacent modules when needed, providing flexible and dynamic memory access capability.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250356894A1Apparatus and methods for decoder modules for non-volatile memory
Publication Date: 2025.11.20 SANDISK TECHNOLOGIES LLC
  • US20250356894A1 patent drawing
  • US20250356894A1 patent drawing
  • US20250356894A1 patent drawing

AI summary

A non-volatile memory includes a memory array having a plurality of non-volatile memory cells, and a first decoder module coupled to the memory array. The first decoder module includes a first plurality of word line decoders coupled to the non-volatile memory cells, a first plurality of bit line decoders coupled to the non-volatile memory cells, a first multiplexor circuit configured to selectively couple one of the first plurality of word line decoders or one of the first plurality of bit line decoders to a positive bias node, and a second multiplexor circuit configured to selectively couple one of the first plurality of word line decoders or one of the first plurality of bit line decoders to a negative bias node. The first multiplexor circuit and the second multiplexor circuit are each coupled to a word line decoder and a bit line decoder outside a boundary of the first decoder module.