Memory Decoder Voltage Staging to Reduce GIDL Leakage
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Solution Overview
Problem
Conventional memory devices experience increased standby current due to gate-induced drain leakage (GIDL) current in transistors, which affects memory chip efficiency.
Innovation Solution
A decoder circuit is designed with series-connected transistors where the voltage at the gate of one transistor is different from another when both are turned off, allowing one transistor to limit the turn-on current and another to reduce the GIDL current, thereby minimizing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional address decoder is used, then the memory can perform data read/write operations, but the gate-induced drain leakage current increases the memory chip standby current
Solution Approach 1:
The patent divides the decoder circuit into multiple transistor stages (first transistor, second transistor, third transistor) with different voltage levels. Each transistor segment handles specific voltage ranges, with the first transistor operating at a first voltage level and the second transistor operating at a second voltage level. This segmentation allows the circuit to maintain proper decoding functionality while reducing GIDL current in each segment.
Solution Approach 2:
The patent applies different voltage levels to different parts of the decoder circuit. The first transistor receives a first control signal at a first voltage level, while the second transistor receives a second control signal at a second voltage level. This local quality differentiation ensures that each transistor operates in an optimal regime that minimizes GIDL current while maintaining decoding reliability.
2Ease of operation
If transistors are used in the decoder, then the decoding function is achieved, but GIDL current occurs causing larger standby current
Solution Approach 1:
The patent changes the voltage parameter of the control signals applied to different transistors. The first transistor is controlled by a signal at a first voltage level, while the second transistor is controlled by a signal at a second voltage level. This parameter change optimizes the operating point of each transistor to minimize GIDL current while maintaining the necessary decoding functionality.
Solution Approach 2:
The patent introduces an intermediate transistor (second transistor) between the first transistor and the third transistor. This intermediary transistor acts as a buffer that operates at an intermediate voltage level, reducing the voltage stress on individual transistors and thereby reducing GIDL current while maintaining the decoding function.
Data Source
AI summary
A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a second terminal of the first transistor are coupled to a first voltage and a first terminal of the second transistor respectively. First terminals and second terminals of the third transistor and the fourth transistor are coupled to a second terminal of the second transistor and a second voltage respectively. When the first transistor and the second transistor are turned off, a voltage of the second control signal is lower than a voltage of the first control signal. Thereby, a gate-induced drain leakage (GIDL) current of the transistors is reduced.