Memory Decoder Iterative Check Logic for Faster Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing bit error rate in memory devices due to higher integration and bit density is not adequately addressed by traditional error correction methods like BCH, necessitating improved decoding techniques for enhanced data reliability.
Innovation Solution
Implementing a decoder that performs incremental check computations using a check matrix and flag matrix to determine successful decoding earlier, reducing redundant error flipping and decoding time through iterative checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional BCH algorithm is used for error correction, then device complexity is reduced, but data reliability deteriorates due to inadequate error correction capability
Solution Approach 1:
The decoder is divided into multiple processing units including syndrome computation units, flag matrix generation units, and iterative check units. Each unit handles specific aspects of the decoding process, allowing parallel processing and reducing the complexity of any single component while maintaining overall high error correction capability.
Solution Approach 2:
The decoder implements dynamic iterative checking where the number of iterations and processing depth are adjusted based on the syndrome results. The system performs initial checks, and only proceeds to deeper iterative checks when errors are detected, making the complexity adaptive rather than static.
2Reliability
If exhaustive error checking is performed to ensure data reliability, then data reliability is improved, but decoding time increases
Solution Approach 1:
The decoder performs preliminary syndrome computation and initial error checks before committing to full iterative decoding. By computing syndromes first and checking simple error patterns early, the system can quickly identify and correct simple errors without performing time-consuming exhaustive checks.
Solution Approach 2:
The decoder uses feedback from syndrome computation results to dynamically adjust the decoding strategy. When syndromes indicate no errors or simple errors, the system terminates early. When syndromes indicate complex errors, the system activates full iterative checking, optimizing the balance between reliability and decoding time based on actual error conditions.
3Reliability
If multiple iterative checks are performed to reduce redundant error flipping, then data reliability is improved, but device complexity increases
Solution Approach 1:
The iterative checking process is segmented into distinct stages: syndrome computation, flag matrix generation, error identification, and correction verification. Each stage is handled by specialized processing units that can be independently optimized and implemented, reducing the structural complexity of the overall system.
Solution Approach 2:
Flag matrices are introduced as intermediary data structures that mediate between the syndrome computation and the error correction steps. These flag matrices efficiently encode error pattern information and guide the iterative checking process, reducing the complexity of direct syndrome-to-correction mapping while improving reliability.
Data Source
AI summary
Examples of the present disclosure disclose a decoder, a decoding method, a memory system, a memory controller, and a computer readable storage medium. The decoder includes a data processing circuit and a data output circuit. The data processing circuit is configured to: perform a current check computation using a current column of a check matrix and a current submatrix of a current flag matrix, wherein the check matrix includes n columns, n being an integer greater than 1; the current flag matrix includes n submatrices, and the current submatrix is related to a current data block of a flipped code word.