Memory Decoder Mode Switching for Error Correction and Speed
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Solution Overview
Problem
Existing decoding methods for rewritable non-volatile memory modules face challenges in balancing error correction ability and decoding speed, leading to inefficiencies in data retrieval.
Innovation Solution
A decoding method and memory control circuit unit that support multiple decoding modes, where decoding modes correspond to threshold values, allowing for dynamic selection based on a relative numerical relationship between decoding parameters and threshold values to optimize error correction and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single decoding mode is used with high error correction ability, then error correction capability is improved, but decoding speed deteriorates
Solution Approach 1:
The patent implements multiple decoding modes (first decoding mode and second decoding mode) that can be dynamically switched based on decoding parameters. The decoding circuit transitions from a static single-mode design to a dynamic multi-mode design, allowing adaptation between error correction capability and decoding speed based on real-time data conditions.
Solution Approach 2:
The patent changes decoding parameters (such as threshold values, iteration counts, and decoding algorithms) to switch between different decoding modes. By adjusting these parameters based on the decoding parameter obtained from initial decoding, the system optimizes the balance between error correction ability and decoding speed for different data conditions.
2Adaptability or versatility
If multiple decoding modes are supported with different threshold values, then adaptability to different error conditions is improved, but device complexity increases
Solution Approach 1:
The patent segments the decoding process into multiple distinct modes (first decoding mode, second decoding mode, etc.), each with specific threshold values and error correction capabilities. This segmentation allows the complex decoding task to be divided into manageable modes that can be selected based on error conditions, reducing the complexity burden compared to a single monolithic decoder.
Solution Approach 2:
The decoding circuit is designed with multi-functionality to support multiple decoding modes within a single unified structure. Rather than implementing separate decoding circuits for different modes, the patent creates a universal decoding circuit that can operate in different modes by adjusting parameters, thereby reducing overall device complexity while maintaining adaptability.
3Productivity
If dynamic selection of decoding mode is implemented based on decoding parameters, then decoding efficiency is improved, but control complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the decoding parameter obtained from the first decoding operation is used to determine the appropriate second decoding mode. This feedback loop allows the system to automatically adjust the decoding mode based on actual decoding results, improving efficiency while keeping control logic manageable through systematic decision rules.
Solution Approach 2:
The patent performs a preliminary first decoding operation to obtain decoding parameters before selecting the final second decoding mode. This preliminary action provides necessary information for mode selection, allowing the system to make informed decisions about which decoding mode to use, thereby improving overall decoding efficiency without excessive control complexity.
Data Source
AI summary
A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.