Memory Decoder Pass Transistors with Varying Channel Dimensions
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Solution Overview
Problem
As memory devices are scaled down, the resistances of bit lines and word lines increase, leading to differences in line resistances among memory cells due to varying lengths, causing issues in programming current application and potential over-programming.
Innovation Solution
The use of pass transistors with varying channel widths and lengths, and diodes of different resistances to compensate for the differences in line resistances among memory cells, ensuring consistent current distribution and preventing over-programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If memory devices are scaled down, then device density is improved, but line resistance increases
Solution Approach 1:
The patent applies local quality by making pass transistors have different channel dimensions based on their specific location in the decoder. Memory cells farther from the decoder have higher line resistance, so their corresponding pass transistors have larger channel widths and/or shorter channel lengths to compensate. This localized adaptation ensures consistent current distribution across all memory cells despite varying line resistances.
2Ease of manufacture
If pass transistors have uniform channel dimensions, then manufacturing is simplified, but current distribution becomes inconsistent
Solution Approach 1:
The patent implements local quality by varying the channel dimensions of pass transistors according to their position. Pass transistors controlling memory cells with higher line resistance (those farther from the decoder) have larger channel widths and/or shorter channel lengths. This creates a gradient in transistor dimensions across the decoder, optimizing current distribution while maintaining manufacturability through systematic dimensional variations.
3Reliability
If line resistance varies across memory cells, then programming accuracy deteriorates, but adding compensation structures increases device complexity
Solution Approach 1:
The patent applies parameter changes by systematically varying the channel width and/or channel length parameters of pass transistors based on their location. This creates a controlled gradient in transistor characteristics that compensates for the natural variation in line resistance across the memory array, ensuring uniform current distribution and accurate programming without requiring complex additional compensation circuits.
Data Source
AI summary
An integrated circuit memory device includes a memory cell array comprising memory cells having respective data storage regions therein, a plurality of pass transistors having different channel widths and/or channel lengths, and a plurality of conductive lines. Each of the conductive lines electrically couple a respective one of the pass transistors to ones of the memory cells. Each of the memory cells has a line resistance defined by a portion of the corresponding one of the conductive lines extending between the memory cell and the pass transistor coupled thereto. Ones of the memory cells having greater line resistances are coupled to ones of the pass transistors having greater channel widths and/or shorter channel lengths than ones of the memory cells having smaller line resistances. Each of the memory cells may also include a diode therein, and ones of the memory cells having greater line resistances may include diodes having lower resistances. Related devices are also discussed.