Memory Decoder Power Allocation for High-RBER Read Throughput
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Solution Overview
Problem
Current memory systems face challenges in maintaining optimal read performance due to static power allocation strategies that fail to adapt to varying raw bit error rates (RBER) in higher-order NAND memory products like TLC and QLC, leading to inefficiencies and compromised processing throughput.
Innovation Solution
Implementing a decoder system with two decoder engines that dynamically allocates power credits based on error pattern detection, allowing the second decoder engine to operate at higher frequencies when errors are detected, prioritizing error correction and maintaining desired quality of service (QoS).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If static power allocation is used for decoder operation, then power management is simplified, but read performance deteriorates due to inability to adapt to varying RBER conditions
Solution Approach 1:
The patent implements dynamic power allocation that adjusts decoder operating frequency based on detected error patterns. The system transitions from static to dynamic operation by monitoring RBER conditions and adapting power credits allocation in real-time, allowing the decoder to operate at optimal frequencies matching current error conditions.
Solution Approach 2:
The system changes operational parameters (power credits, operating frequency) based on detected error patterns. When high RBER is detected, the system allocates additional power credits to increase decoder frequency and processing capability, directly linking parameter adjustment to performance optimization.
2Reliability
If decoder operates at higher frequency to correct errors, then error correction capability improves, but power consumption increases
Solution Approach 1:
The patent implements dynamic frequency scaling where the decoder operates at higher frequencies only when error patterns indicate high RBER conditions. When error rates are low, the system reduces operating frequency to conserve power, creating a dynamic balance between reliability and energy consumption.
Solution Approach 2:
The system adjusts power credits allocation based on detected error patterns, directly linking power consumption to actual error correction needs. This parameter change ensures power is consumed at higher levels only when reliability requirements demand enhanced error correction capability.
3Device complexity
If static power allocation is used, then power management is simpler, but processing throughput deteriorates under high RBER conditions
Solution Approach 1:
The patent implements dynamic power allocation that responds to error pattern detection, allowing the system to optimize processing throughput under varying RBER conditions. The dynamic adjustment of power credits enables the decoder to scale processing capability matching actual workload demands.
Solution Approach 2:
The system incorporates feedback mechanisms that monitor error patterns and RBER conditions, using this information to adjust power allocation and processing frequency. This closed-loop control ensures processing throughput is optimized based on actual error conditions rather than static pre-configuration.
Data Source
AI summary
Methods, systems, and devices to enhance read performance for memory data word decoding using power allocation based on error pattern detection in both QLC and TLC in both QLC and TLC products are described. A plurality of data words may be processed using a first decoder engine of a decoder of a memory device according to a first power setting. The decoder may detect a pattern of errors in the plurality of data words. The decoder may further communicate a status signal based on detecting the pattern of errors. The resource manager may allocate based on the status signal, a second amount of power credits to the decoder. The decoder may process a portion of the plurality of data words using a second decoder engine according to the second amount of power credits.