Memory Decoder Power Gating to Prevent Leakage in Idle Blocks
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Solution Overview
Problem
Existing memory devices face issues with power consumption and stability in column decoder circuits due to continuous power supply to non-enabled states, leading to signal leakage and interference, which affects circuit performance and data integrity.
Innovation Solution
A decoder circuit with a power supply control circuit using transistors and a reverse circuit to manage power supply and grounding interfaces based on the enabled state of memory blocks, ensuring normal power supply only to enabled states and floating interfaces in non-enabled states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous power supply is provided to column decoder circuits, then circuit operation is maintained, but power consumption increases and signal leakage occurs
Solution Approach 1:
The patent applies dynamic power supply control by transitioning the power supply state from static (continuous) to dynamic (conditional). The column decoder circuit receives power supply signals that are dynamically adjusted based on the enabled state of memory blocks, allowing the circuit to adapt its power consumption level to operational requirements.
Solution Approach 2:
The patent implements periodic power supply action through the power supply control circuit, which periodically activates or deactivates power supply to the column decoder circuit based on memory block enabled states. This periodic control mechanism ensures power is supplied only when needed, reducing continuous power consumption while maintaining operational reliability.
2Ease of operation
If continuous power supply is provided to non-enabled states, then circuit remains ready, but signal leakage and interference increase
Solution Approach 1:
The patent extracts the power supply control function from the main column decoder circuit by implementing a separate power supply control circuit. This extracted control mechanism independently manages power supply to the column decoder based on memory block enabled states, removing the harmful effect of continuous power supply to non-enabled circuits while maintaining readiness for enabled blocks.
Solution Approach 2:
The power supply control circuit serves as an intermediary between the memory block enabled state and the column decoder circuit power supply. This intermediary component translates the enabled state information into appropriate power supply signals, ensuring that power is supplied only to circuits that need to operate, thereby eliminating signal leakage from non-enabled circuits.
3Use of energy by moving object
If power supply interfaces are floated in non-enabled states, then power consumption reduces, but circuit stability must be maintained
Solution Approach 1:
The patent segments the power supply control into separate control paths for different memory block enabled states. The power supply control circuit independently manages power supply to different column decoder circuits based on their corresponding memory block states, allowing non-enabled circuits to have their power supply interfaces floated while enabled circuits maintain stable power supply, thus reducing overall power consumption without compromising circuit stability.
Data Source
AI summary
Decoder circuit, memory device, and control method are disclosed. The decoder circuit includes a decoding circuit and a power supply control circuit including: a first transistor, its input is connected to a low-level voltage node, and its output outputs a first ground voltage; a second transistor, its input is connected to a high-level voltage node, and its output outputs a first voltage; and a reverse circuit, its input receives a semiconductor component enabling signal, and its output is connected to the control terminal of one of the first or second transistor; and the control terminal of the first or second transistor not connected to the reverse circuit receives the semiconductor component enabling signal. The decoding circuit includes sub-circuits, wherein a power supply interface of sub-circuit is connected to the output of second transistor, or a grounding interface of sub-circuit is connected to the output of first transistor.