Memory Decoder Circuit Segmentation for Power and Area Reduction

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Solution Overview

Problem

Conventional memory circuits face challenges in reducing power consumption during read operations while maintaining high voltage requirements for modify operations, often relying on charge pumps that increase power consumption and circuit area.

Innovation Solution

A decoder circuit utilizing high voltage and low voltage transistors, where high voltage transistors provide necessary voltages during modify operations and low voltage transistors enhance read operation speed without the need for a charge pump, reducing power consumption and circuit area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a charge pump is used to provide boosted voltage during read operations, then the speed of read operations increases, but power consumption increases

Engineering Contradiction:

Improveread operation speedVSAvoidpower consumption during read operations

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The decoder circuit is segmented into two distinct paths: a first decoder path using high voltage transistors for modify operations, and a second decoder path using low voltage transistors for read operations. This segmentation allows each path to be optimized for its specific function without requiring a charge pump during read operations, thus improving read speed while reducing power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different voltage characteristics are applied to different functional paths within the decoder circuit. The first decoder path uses high voltage transistors optimized for modify operations requiring boosted voltage, while the second decoder path uses low voltage transistors optimized for read operations where high speed is prioritized over voltage boosting capability.

Inventive Principle:

Principle #3Local quality

2Reliability

If high voltage transistors are used during modify operations to provide boosted voltage, then modify operation capability is maintained, but circuit area increases

Engineering Contradiction:

Improvemodify operation capabilityVSAvoiddecoder circuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The decoder circuit is divided into separate functional paths, with high voltage transistors confined to the first decoder path only when needed for modify operations. The second decoder path uses compact low voltage transistors, reducing the overall area while maintaining modify operation capability through the segmented architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The decoder circuit dynamically switches between using the first decoder path with high voltage transistors during modify operations and the second decoder path with low voltage transistors during read operations. This dynamic switching allows the circuit to maintain modify operation capability only when necessary, reducing the effective area requirement.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8837252B2Memory decoder circuit

Publication Date: 2014.09.16 ATMEL CORP

AI summary

A decoder circuit includes high voltage and low voltage transistors. The decoder circuit uses the high voltage transistors during modify operations to provide a high voltage, e.g., a boosted voltage, to memory cells to change memory cell status or perform other operations. The decoder circuit uses the low voltage transistors during read operations.