Memory Array Decoder Circuitry Vertical Integration
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Solution Overview
Problem
Conventional memory chip designs with tiled architectures face challenges in die area savings and increased fabrication complexity, while maintaining access speeds and reducing resistance in wordlines and bitlines.
Innovation Solution
Placing row and column decoder circuitries under or adjacent to the memory array, along with other peripheral components like the memory control unit and I/O circuitry, to increase packing density and simplify die fabrication, potentially using lower resistance materials for bitlines and wordlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If decoder circuitries are placed laterally adjacent to the memory array in conventional tiled architectures, then access speeds are maintained, but die area increases and fabrication complexity increases
Solution Approach 1:
The patent moves the decoder circuitries from a lateral position (in the plane of the array) to a position underneath the memory array, utilizing the vertical dimension. This dimensional transition allows the decoders to be integrated into the array footprint, reducing the overall die area while maintaining electrical connection for access speed performance.
Solution Approach 2:
The decoder circuitries are nested underneath the memory array structure, with the decoders positioned in the vertical space below the array. This nesting arrangement allows compact integration where the decoders are contained within the vertical profile of the array rather than occupying additional lateral space.
2Speed
If decoder circuitries are placed laterally adjacent to the memory array, then access speeds are maintained, but fabrication complexity increases
Solution Approach 1:
The patent merges the decoder circuitries with the memory array by positioning them underneath the array structure. This consolidation integrates multiple functional blocks (array and decoders) into a unified structure, simplifying the fabrication process by reducing the number of separate components and interconnections that would otherwise be required in a tiled lateral arrangement.
Solution Approach 2:
By transitioning the decoder placement to the vertical dimension (underneath the array), the patent simplifies fabrication by eliminating complex lateral routing and alignment requirements between separately fabricated decoder tiles and array tiles, reducing overall fabrication complexity.
3Ease of manufacture
If conventional tiled architecture is used, then manufacturing process is standardized, but die area increases and fabrication complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by placing decoder circuitries underneath the memory array, transforming the conventional lateral tiled layout into a stacked configuration. This dimensional change reduces die area by eliminating lateral expansion while maintaining manufacturing feasibility through standardized vertical integration processes.
4Productivity
If more dice are produced from a single wafer, then productivity increases, but die fabrication complexity must be reduced
Solution Approach 1:
By merging the decoder circuitries with the memory array into a single integrated structure positioned underneath, the patent reduces die fabrication complexity. This consolidation allows for simpler wafer-level processing and testing, enabling higher yields and more dice per wafer by reducing the complexity of individual die fabrication and assembly.
Solution Approach 2:
The vertical integration of decoders underneath the array simplifies the die structure, making it more amenable to high-volume manufacturing. This dimensional reorganization reduces fabrication complexity by eliminating complex lateral interconnections, thereby increasing productivity through higher dice per wafer production.
Data Source
AI summary
Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.