Nonvolatile Memory Decoder Voltage Segmentation for High-Speed Read
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Solution Overview
Problem
High withstand voltage circuits in nonvolatile semiconductor memory devices slow down the reading of information from memory cells due to thick gate insulation films, making it difficult to read data at high speeds.
Innovation Solution
The use of low voltage circuits for the column decoder and second row decoder allows for high-speed operation of selecting transistors, while high voltage circuits for the first row decoder and third row decoder ensure sufficient withstand voltage, enabling faster read operations without compromising data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high withstand voltage circuits are used for all decoders, then circuit integrity is ensured, but reading speed decreases due to thick gate insulation films
Solution Approach 1:
The patent applies different voltage circuit designs to different decoder locations. Specifically, the column decoder and second row decoder use low withstand voltage circuits optimized for speed, while the first row decoder and third row decoder use high withstand voltage circuits optimized for reliability. This local differentiation resolves the contradiction by matching circuit characteristics to functional requirements in each region of the memory device.
2Speed
If low voltage circuits are used for column decoder and second row decoder, then reading speed increases, but voltage control capability for selected memory cells may be insufficient
Solution Approach 1:
The patent segments the voltage control function across multiple decoders with different characteristics. The column decoder and second row decoder (low voltage) handle row/column selection and initial control, while the first row decoder and third row decoder (high voltage) provide the necessary high voltage control for memory cell operation. This segmentation allows speed optimization in selection circuits while maintaining voltage control capability in memory control circuits.
Data Source
AI summary
A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.