3D Memory Decoding Circuit with Paired Triple-Well Transistors
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Solution Overview
Problem
Current memory technologies face challenges in enhancing storage density and performance, particularly in meeting future system requirements with existing 3D memory solutions.
Innovation Solution
A memory device comprising a memory array, a decoding circuit with paired triple-well transistors, and a controller, where the transistors are coupled to local bit lines and source lines, and global bit and source lines, allowing for efficient control and voltage management to prevent body effect and enhance programming speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistors are used in 3D memory, then manufacturing is simpler, but body effect occurs causing reduced programming speed and efficiency
Solution Approach 1:
The patent changes the transistor structure from conventional to triple-well transistors, modifying the physical parameters of the device to eliminate body effect and improve programming speed while maintaining compatibility with existing 3D memory architectures
Solution Approach 2:
The patent uses paired transistors (first and second transistors) that are symmetrically configured, where each transistor pair controls complementary signals (bit line and source line) to achieve balanced performance and eliminate body effect through symmetric current paths
2Productivity
If paired transistors control local bit lines and source lines, then body effect is eliminated, but device complexity increases
Solution Approach 1:
The patent segments the control function by dividing bit lines and source lines into local lines controlled by paired transistors and global lines for voltage distribution. This segmentation allows independent control of signal paths while maintaining modular architecture that reduces overall system complexity
Solution Approach 2:
The paired transistors serve multiple functions: they control signal transmission, eliminate body effect, and provide symmetric current paths. The same transistor pair structure is reused across multiple bit lines and source lines, achieving universal applicability without proportionally increasing complexity
3Reliability
If triple-well transistors are used, then body effect is prevented, but manufacturing precision requirements increase
Solution Approach 1:
The patent modifies the transistor fabrication parameters by introducing triple-well structures with specific doping concentrations and depths. These parameter changes enable body effect elimination while the standardized well depth and doping levels maintain compatibility with existing manufacturing processes
Solution Approach 2:
The patent applies different doping characteristics to different regions of the triple-well transistor structure. The well regions have specific doping levels optimized for body effect elimination, while the channel regions have doping tailored for optimal transistor performance, allowing localized optimization without compromising overall manufacturing feasibility
Data Source
AI summary
A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.