Memory Word Line Decoding With Repeaters for Faster Address Setup
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines within these digital devices affects the operating voltages and overall performance, necessitating improvements in timing and signal integrity.
Innovation Solution
A memory circuit design that includes a global control circuit generating pre-decoder signals and local control circuits with repeater circuits to enhance the driving strength of local pre-decoder signals, improving address setup time through increased signal propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the memory circuit is scaled down to reduce size, then device integration is improved, but conductive line resistance increases affecting operating voltage and performance
Solution Approach 1:
The memory circuit is divided into multiple blocks, each with its own local control circuit and repeater circuits. This segmentation allows signal regeneration at intermediate points, compensating for resistance effects in scaled-down conductive lines while maintaining overall device compactness
Solution Approach 2:
Repeater circuits are introduced as intermediary elements between the global control circuit and memory blocks. These repeaters amplify and regenerate pre-decoder signals, acting as mediators that compensate for signal degradation caused by high resistance in miniaturized conductive lines
2Loss of time
If repeater circuits are added to enhance signal driving strength, then address setup time is improved, but device complexity increases
Solution Approach 1:
The control functionality is segmented between a global control circuit for high-level coordination and local control circuits within each memory block for signal regeneration. This segmentation distributes complexity across multiple simple units rather than concentrating it in a single complex circuit, improving address setup time while managing overall device complexity
Solution Approach 2:
Each memory block contains its own local control circuit and repeater circuits that autonomously regenerate and amplify signals as needed. This self-service approach allows each block to compensate for signal degradation independently, reducing the need for complex global signal management and improving address setup time
Data Source
AI summary
A memory circuit includes a global control circuit, a first local control circuit and a first set of word line post-decoder circuits. The global control circuit is configured to generate a first and second set of global pre-decoder signals and a first set of local address signals. The first local control circuit includes a first set of repeater circuits and a first clock pre-decoder circuit. The first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. The first clock pre-decoder circuit is configured to generate a first and second set of clock signals. The first set of word line post-decoder circuits is configured to generate a first set of word line signals.